| MEMORY_TEST Project Status | |||
| Project File: | Memory_test.ise | Current State: | Programming File Generated |
| Module Name: | Block_Ram_Test |
|
No Errors |
| Target Device: | xc2s100-5tq144 |
|
16 Warnings |
| Product Version: | ISE, 8.1i |
|
Thu Feb 16 10:51:30 2006 |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 38 | 2,400 | 1% | |
| Number of 4 input LUTs | 12 | 2,400 | 1% | |
| Logic Distribution | ||||
| Number of occupied Slices | 26 | 1,200 | 2% | |
| Number of Slices containing only related logic | 26 | 26 | 100% | |
| Number of Slices containing unrelated logic | 0 | 26 | 0% | |
| Total Number 4 input LUTs | 48 | 2,400 | 2% | |
| Number used as logic | 12 | |||
| Number used as a route-thru | 36 | |||
| Number of bonded IOBs | 7 | 92 | 7% | |
| Number of Block RAMs | 1 | 10 | 10% | |
| Number of GCLKs | 1 | 4 | 25% | |
| Number of GCLKIOBs | 1 | 4 | 25% | |
| Total equivalent gate count for design | 16,976 | |||
| Additional JTAG gate count for IOBs | 384 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | Thu Feb 16 10:51:10 2006 | 0 | 16 Warnings | 0 |
| Translation Report | Current | Thu Feb 16 10:51:14 2006 | 0 | 0 | 0 |
| Map Report | Current | Thu Feb 16 10:51:17 2006 | 0 | 0 | 2 Infos |
| Place and Route Report | Current | Thu Feb 16 10:51:22 2006 | 0 | 0 | 2 Infos |
| Static Timing Report | Current | Thu Feb 16 10:51:24 2006 | 0 | 0 | 2 Infos |
| Bitgen Report | Current | Thu Feb 16 10:51:30 2006 | 0 | 0 | 0 |