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Course Objectives

Prerequisites

Approach

Typical Text

Course Outline

Course Objectives
Develop an understanding of the architecture and implementation of von Neumann computer systems. Understand the interdependence of architectural and implementation decisions through the detailed examination of one simple, complete computer.

Prerequisites
COMP 411 and digital logic (PHYS 352)

Approach
Study architecture by topics, using relevant portions of various real computers to illustrate each topic. Study implementation chiefly through the detailed examination of one simple, complete computer. Supplement the textbook with selected readings from the literature. Do not emphasize programming or hardware laboratory.

Typical Text
Hennessy and Patterson, Computer Architecture: A Quantitative Approach (2nd edition), Chapters 1-6.

Course Outline
Numbers in parentheses indicate approximate number of weeks

• Basics of machine organization (review) (0.5)
  • CPU
  • Control Unit: hardwired and microprogrammed
  • Memory
  • I/O: CPU-controlled and autonomous

• Principles of instruction set design (1.5)
  • Instruction formats
  • Memory addressing
  • Types of instruction operators (including synchronization primitives, and their implementations on pipelined Load / Store machines)
  • Sizes of operands
  • How programs (and machines) behave--dynamic frequencies

• Computer arithmetic (1)
  • Fast add, multiply and divide units
  • Floating point arithmetic and the IEEE Floating Point Standard

• Pipelining (instruction level parallelism) (4)
  • Basics: notations, speedup, classification of pipelines
  • Instruction pipelining
    • Hazards: structural, data and control hazards
    • Hardware solutions: interlocks, forwarding, renaming, branch prediction
    • Software solutions: pipeline scheduling, loop unrolling, software pipelining
  • Out of order execution, speculative execution and precise interrupts
  • Multiple issue (superscalar and VLIW) processors
  • Vector processors

• Memory hierarchy (3.5)
  • Cache memory
    • Addressing methods
    • Fetch, write and replacement policies
    • Split and unified caches
    • Multilevel caches
    • Physical and virtual caches
  • Main memory
    • DRAM technology
    • Increasing bandwidth: interleaving, DRAM-specific techniques
  • Virtual memory
    • Methods of address translation
    • Translation Lookaside Buffers

• Autonomous I/O (1)
  • I/O and cache: cache coherence, bus-based or snoopy coherence protocols
  • I/O and virtual memory

• Quantitative characterizations of CPU, memory and I/O performance (1.5)
  • Quantitative principles of computer design
  • Measuring and reporting performance