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Patent Number: 6,131,078
Date of Patent: 10 October 2000
Inventors: Plaisted; David A. (Chapel Hill, NC)
Assignee:
Appl. No.: 09/339,091
Filed: June 23, 1999
Int. Cl.: G06F 17/10 (20060101); G06F 017/10
U.S. Cl.: 703/2 ; 716/5
17 Claims

Abstract
A computer implemented method for verifying that a circuit or other system satisfies its specifications, is based on creating a first Boolean formula G representative of the system and its specification and through a series of steps creating a second formula G' having a known logical relationship to G and using the second formula G' to determine whether the system satisfies its specification.