Programming the Network Data Plane in P4
Software-Defined Networking (SDN) has been successful because it lets network owners and operators "program" network behavior. SDN's programmability, however, is confined to the network control plane today. The forwarding plane is still largely dictated by fixed-function packet-processing hardware. Our goal is to change that, and to allow programmers to define how packets are to be processed all the way down to the wire. This is made possible by a new generation of high-performance forwarding chips. At the high-end, switching chips built with a new machine architecture -- namely PISA (Protocol-Independent Switch Architecture) -- promise multi-Tb/s of packet processing. At the mid- and low-end of the performance spectrum, CPUs, GPUs, FPGAs, and NPUs already offer great flexibility with performance of a few tens to hundreds of Gb/s. In addition to programmable forwarding chips, we also need a high-level language to dictate the forwarding behavior in a target independent fashion. "P4" (www.p4.org) is such a language. In P4, the programmer declares how packets are to be processed, and a compiler generates a configuration for a PISA chip, or a programmable target in general. In this talk, I will first give a quick overview of PISA and explain why it is inevitable; within the next couple of years I expect all switching chips to be programmable, with no performance, power or cost penalty. I will then give a brief primer on the P4 language, showing some example programs for a variety of different networks, demonstrating the power of writing portable and reusable P4 programs. Finally I will introduce a few exciting use cases that data-plane programmability can enable, along with new challenges and problems warranting further study.
Recorded April 21, 2017