Enabling Next-Generation Multicore Platforms in Embedded Applications

Principal Investigator: James Anderson
Funding Agency: Air Force Research Laboratory
Agency Number: FA8750-11-1-0033

Abstract
The last few years has seen a proliferation of multicore-based products in the home computing and server markets. Now, the same is happening in the embedded arena. Multicore platforms offer greater computational capacity, with less space, cabling, and power consumption, and thus have the potential of enabling a new generation of sophisticated embedded devices. However, the shift to multicore technologies has created new challenges from a software design perspective due to the need to manage parallelism. Additionally, consolidating different system components on a common multicore platform-instead of using many, connected processors, as is often done in embedded designs-requires mechanisms for temporally, logically, and securely isolating components, and such isolation is not straightforward to ensure. Eventually, physical limitations will restrict per-chip core counts. When this happens, chip makers will distinguish themselves not by offering more or faster (general-purpose) cores, but by offering specialized hardware components that accelerate certain computations. A computing platform such as this with specialized components is called a heterogeneous platform. Even now, heterogeneity exists at different levels in many commercial systems. One of the earliest notable examples of this was the IBM Cell Broadband Engine, which has a general-purpose CPU and eight special-purpose processing units on the same chip. More recently, many chip makers have been espousing GPGPU configurations as the new "standard computing platform"—in such a configuration, a general purpose (GP) machine, with one or more cores, is paired with a sophisticated graphics processing unit (GPU), which may consist of many cores. Such configurations are part of a continuing evolution of co-processor-based designs; systems with digital signal processors (DSPs) or field-programmable gate arrays (FPGAs) as co-processors have been, and continue to be, in widespread use. Unfortunately, heterogeneity makes multicore-related programming challenges even more difficult. Efficiently utilizing a multicore platform requires judicious resource allocation. Resource allocation problems are notoriously harder (and often provably so) when choices must be made involving resources with different capabilities. In this project, we intend to consider such problems, and related programming challenges, in the context of embedded computing systems. Our specific goal is to develop real-time operating-system (RTOS) infrastructure that allows embedded multicore computers to be efficiently utilized, enables rigorous validation of timing correctness, and allows different system components to be securely isolated. Our research agenda is relevant to multicore based systems generally, though issues pertaining to heterogeneity are a particular emphasis.