High-Speed Asynchronous Pipeline Technology for the DARPA CLASS Project

Principal Investigator: Montek Singh 
Funding Agency: DARPA (indirect The Boeing Company) 
Agency Number: KT3408

Abstract

The objective of CLASS is to develop tools and techniques to enable rapid design of high-speed and energy-efficient electronic chips. The expected legacy of CLASS is a commercial-strength CAD tool that uses automation techniques to drastically cut down chip development time, and yet provide speed and energy performance that is superior to current practices. Novelty: The key differentiator of the CLASS CAD tool will be the use of "asynchronous" or "clockless" circuit design techniques. In contrast, current industry practice is dominated by (over 99%) "synchronous" or "clocked" circuit design. The belief that asynchrony has significant advantages over current synchronous approaches is fast gaining momentum. However, asynchronous design has hitherto only been pursued by universities or research labs. This DARPA-sponsored project seeks to push asynchronous design into the mainstream. The PI and his research team will supply high-speed asynchronous pipelined circuit design technology that is critical for the CAD tool. This technology is also sometimes referred to as "high-speed pipelines," "circuit technology," "logic technology," or "logic configuration," by various parties in different contexts.