Power Aware Graphics Hardware

Principal Investigator: Anselmo Lastra, Montek Singh
Funding Agency: National Science Foundation
Agency Number: CCF-0702712

Abstract
We propose revolutionary changes to graphics accelerators for handheld devices by using asynchronous logic to enable a more efficient pipeline. There are many advantages to clockless logic, including automatic power-down. Since there’s no clock, when there’s no work the power consumption is minimal. For graphics pipelines we foresee other advantages, such as variable-precision computation - use only as many bits as necessary - and data-dependent computation. The expected result: higher performance for less power.