VLSI graphics display image buffer using logic enhanced pixel memory cells
Patent Number: 4,783,649
Date of Patent: Nov. 8, 1988
Inventors: Henry Fuchs (Pittsboro, N.C.); John W. Poulton (Durham, N.C.)
Assignee: The University of North Carolina at Chapel Hill, Chapel Hill, N.C.
Appl. No.: 408,045
Filed: Aug. 13, 1982
Int. Cl.: G09G 1/16
U.S. Cl.: 340/747
7 Claims
Abstract
A VLSI graphics display image buffer which enables the graphics display system of Fuchs U.S. Pat. No. 4,590,465, to be economically realized. According to the present invention, the X and Y multiplier trees disclosed in Fuchs U.S. Pat. No. 4,590,465, can be combined into a single tree and connected to an IC memory grid of conventional design. Special memory chips of this design are then much like conventional RAM chips with only a small amount of additional logic circuitry. However, the standard grid of memory cells on such a chip is organized so that each row of memory cells corresponds to the different bits of the single pixel, whereas each column is the corresponding bit in every pixel. Each output of the X-Y multiplier tree is then available to the circuitry associated with a particular pixel and its row of memory cells. These VLSI chips can be organized so that the system can be implemented by a set of identical chips that need no special interconnection. All control and data input signals may be broadcasted to the chips by simulating on each chip the top parts of the X-Y multiplier tree. In other words, the simulated tree levels are loaded with the high order bits of the X and Y addresses of the screen area represented by the pixels of the particular chip.