Does it really take longer to send a bit from one chip to another than to do a 64-bit addition? We don't think so.
The performance of many digital systems is limited by the interconnection bandwidth between chips, boards, and cabinets. As VLSI technology continues to scale, system bandwidth will become an even more significant bottleneck because off-chip signaling rates have historically scaled more slowly than on-chip clock rates. Most digital systems today use full-swing unterminated signaling methods that are unsuited for data rates over 100MHz on 1m wires. Even good current-mode signaling methods with matched terminations and carefully controlled line and connector impedance are limited to about 1 GHz by the frequency-dependent attenuation of copper lines. Without new approaches to high-speed signaling, bandwidth will stop scaling with technology when we reach these limits.
We are working to develop methods and circuits to enable high-speed, low-energy signaling between CMOS integrated circuits. Using 0.5 micron CMOS technology we expect to achieve signaling rates of 4Gb/s over a 3m differential pair between two VLSI chips. Our approach overcomes the limitation of present-day signaling techniques by using pre-emphasis and equalization to compensate for the frequency-dependent attenuation enabling operation at frequencies well above the 3dB point of the line. We also employ a number of novel methods to reduce timing uncertainty and cancel noise. By overcoming a number of fundamental problems in signaling, we expect our methods to enable continued scaling of signaling rates with improvements in IC process technology.
Comparing the potential of a 4 Gb/s link with other signaling schemes in use today shows how dramatically its availability could affect future system designs. A single pair of 4Gb/s links has four times the bandwidth of a 32 bit PCI bus which requires about 80 signals. Substituting this technology for conventional interconnect could convert a chip with 500 signal pins (at 100MHz) to one with 15 signal pairs operating at 4 Gb/s. This will significantly reduce packaging costs, power dissipation, and system noise.
This photograph shows our test chip and board in operation. The oscilloscope shows 10 bits of 4 Gb/s data (250 picoseconds per division). For more information, some of the following pages.
Intel has donated several machines for use by the Stanford members this research team, and Microsoft has donated much of the software running on these machines.
The team is grateful to the free software community for such software as Gnu/Linux and Perl which were invaluable to our work, particularly at UNC.