Selected Bibliography on High-Speed Signaling

• Bakoglu, H., Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, 1990.
• Banu, M., and Dunlop, A., "A 600Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission," IEEE ISSCC93, pp 102-103.
• Bazes, M., "Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers," IEEE JSSC, Vol. 26, No. 2, pp 165-168.
• Bull Serial Link Technology, B.P. 68, PC F1-1D-16, rue Jean-Jaures, 78340 Les Clayes-sous-Bois, France.
• Bursky, D., "High-Speed CMOS I/O Interface Outstrips BTL and GTL Line Drivers," Electronic Design, July 8, 1996, pp 35.
• Chappell, B., et.al., "Fast CMOS ECL Receivers With 100-mV Worst-Case Sensitivity," IEEE JSSC, Vol. 23, No. 1, pp 59-67.
• Chen, D., and Waldron, R., "A Single-Chip 266Mb/s CMOS Transmitter/Receiver for Serial Data Communications," IEEE ISSCC93, pp 100-101, 269.
• Chen, D., and Baker, M., "A 1.25Gb/s, 460mW CMOS Tranceiver for Serial Data Communications," ISSCC97 , pp242-243.
• Choa, H., Robe, T., and Smoot, L., "A 140 Mbint/s CMOS LSI Framer Chip for a Broad-Band ISDN Local Access System," IEEE JSSC, Vol. 23, No. 1, pp 133-141.
• Cordell, R., "A 45-Mbit/s CMOS VLSI Digital Phase Aligner," IEEE JSSC, Vol. 23, No. 2, pp 323-328.
• Dally, W., and Poulton, J., "Transmitter Equalization for 4Gb/s Signalling," Proc. of Hot Interconnects 1996, pp 29-39, Stanford University, Aug 15-17, 1996.  Also in IEEE Micro,  pp 48-56, Jan/Feb, 1997.
• DeHon, A., Knight, T., and Simon, T., "Automatic Impedance Control," IEEE ISSCC93, pp 164-165, 283.
• Dennison, L., Lee, W., and Dally, W., "High-Performance Bidirectional Signalling in VLSI Systems," MIT Artificial Intelligence Laboratory, 1992.
• Dolle, M., "A Dynamic Line-Termination Circuit for Multireceiver Nets," IEEE JSSC,  Vol. 28, No. 12, pp 1370-1373.
• Donnelly, K., et.al., "A 660MB/s Interface Magacell Portable Circuit in 0.3µm- 0.7µm CMOS ASIC," IEEE ISSCC96, pp 290-291.
• Fiedler, A. R. Mactaggart, J. Welch, and S. Krishnan, "A 1.0625 Gbps Tranciever with 2x-Oversampling and Transmit Signal Pre-Emphasis," ISSCC97 ,pp238-239.
• Gabara, T., and Knauer, S., "Digitally Adjustable Resistors in CMOS for High-Performance Applications," IEEE JSSC, Vol. 27, No. 8, pp 1176-1185.
• Gunning, B., et.al., "A CMOS Low-Voltage-Swing Transmission-Line Transceiver," IEEE ISSCC92, pp 58-59.
• Hanafai, H., et.al., "Design and Characterization of a CMOS Off-Chip Driver/Receiver with Reduced Power-Supply Disturbance," IEEE JSSC, Vol. 27, No. 5, pp 783-791.
• Hatakeyama, A., et.al., "A 256Mb SDRAM Using a Register-Controlled Digital DLL," IEEE ISSCC97 , pp 72-73.
• IEEE Std. 1596.3-1996, "Differential Signals (LVDS) For Scalable Coherent Interface (SCI)," pp 5-30.
• Johns, D., and Essig, D., "Integrated Circuits for Data Transmission Over Twisted-Pair Channels," IEEE JSSC, Vol. 32, No. 3, pp 398-406.
• Knight, T., and Krymm, A., "A Self-Terminating Low-Voltage Swing CMOS Output Driver," IEEE JSSC,  Vol. 23, No. 2, pp 457-464.
• Knight, T., and Krymm, A., "Self Terminating Low Voltage Swing CMOS Output Driver," Symbolics, Inc., 1987.
• Lam, K., Dennison, L., and Dally, W., "Simultaneous Bidirectional Signalling for IC Systmes," IEEE 1990, pp 430-433.
• Latif, S., "MIPS R4000 Slew Rate Control Logic for Output Buffers," MIPS Technologies, Inc., 1992.
• Lee, A., and Messerschmitt, G., Digital Communication, Second Edition, Kluwer, 1994.
• Lee, K., et.al., "A CMOS Serial Link for Fully Duplexed Data Communication," IEEE JSSC, Vol. 30, No. 4, pp 353-364.
• Lee, W., Dennison, L., and Dally, W., "Implementation of a Simultaneous Bidirectional I/O Pad for Inter-Chip Communication," 1991.
• Manetis, J., "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE JSSC, Vol. 31, No. 11, pp 1723-1732.
• Manetis, J.,  and Horowitz, M., "Precise Delay Generation Using Coupled Oscillators," IEEE JSSC, Vol. 28, No. 12, pp 1273-1282.
• Marbot, R., et.al., "Integration of Multiple Gigabit per Second Serial Links with Self Test Capability," Bull Systems, 1992.
• Matick, R., Transmission Lines for Digital and Communication Networks, McGraw-Hill, 1969.
• Meylemans, P., et.al., "A Broadband ISDN Line Termination Chip Set for 1.2 Gb/s," IEEE ISSCC93, pp 106-107, 271.
• Montaro, J., et.al., "A 160 MHz, 32-b, 0.5-W CMOS RISC Microprocessor," IEEE JSSC, Vol. 31, No. 11, pp 1703-1714.
• Mooney, R., Dike, C., and Borkar, S., "A 900 Mb/s Bidirectional Signaling Scheme," IEEE JSSC, Vol. 30, No. 12, pp 1538-1546..
• Nakao, T., et.al., "Single-Chip 4-Channel 155 Mb/s CMOS LSI Chip for ATM SONET/SDH Framing and Clock/Data Recovery," IEEE ISSCC97, pp 160-161.
• Ohuchi, M., et.al., "A Si Bipolar 5-Gb/s 8:1 Multiplexer and 4.2-Gb/s 1:8 Demultiplexer," IEEE JSSC, Vol. 27, No. 4, pp 664-673.
• Raver, N., "Open-Loop Gain Limitations for Push-Pull Off-Chip Drivers," IEEE JSSC, Vol. SC-22, No. 2, pp 145-150.
• Senthinathan, R., and Prince, J., "Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise," IEEE JSSC, Vol. 28, No. 12. pp 1383-1388.
• Sidiropoulos, S., Yang, C., and Horowitz, M., "A CMOS 500 Mbps/pin Synchronous Point to Point Link Interface," IEEE 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp 43-44.
• Sidiropoulos, S., and Horowitz, M., "A 700 Mbps/pin CMOS Signalling Interface Using Current Integrated Receivers," Center for Integrated Systmes, Stanford University.
• Song, B., and Soo, D., "NRZ Timing Recovery Technique for Band-Limited Channels," IEEE ISSCC96, pp 194-195.
• Tomlinson, M., "New Automatic Equalizer Employing Modulo Arithmetic," Electronic Letters, March 1971.
• Wu, J., Chang, H., and Chen, P., "A 2V 100MHz CMOS Vector Modulator," IEEE ISSCC97 , pp 80-81.
• Yang, C., and Horowitz, M., "A 0.8-µM CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links," IEEE JSSC, Vol. 31, No. 12, pp
• Yang, C., and Horowitz, M., "A 0.8-µM CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links," IEEE ISSCC96, pp 200-201, 444.
• Yang, C., and Horowitz, M., "A 0.8-µM CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links," IEEE ISSCC96, pp 158-159, 410.