On the left of the test board can be seen three of the test chips, the center area is devoted to control logic, and power supply and PC interface circuitry is on the right.Up to three chips can be installed on the board. One chip has its transmitter and receiver connected by a minimum-length transmission line; the others can be interconnected by 1, 2, or 3 meter PCB traces or by external coaxial or twisted-pair cables. All transmitter outputs and receiver inputs have a resistive probe brought out to SMA connectors for connection to an oscilloscope. A 400 MHz clock from an external signal generator is gated, buffered and distributed to all chips with discrete ECLinPS logic. ECL counters and delay lines allow positioning the trigger signal for the on-chip digital and analog samplers with 20ps resolution 655us of delay range. Oscilloscope trigger outputs at the 400MHz clock rate and at fclk/8 are provided; the former is useful for generating eye diagrams; the latter corresponds to the period of the transmitter's pattern RAM. A 12-bit DAC generates a reference voltage for the analog voltage samplers. Error indications from the reciever on each chip are accumulated in 10 bit counters. The chips' serial scan chains and control signals for the testboard logic are are connected to a host computer through an optically-isolated standard PC parallel port.
The board is connected to the parallel port of a Pentium-Pro PC. Our department has been buying DELL machines recently, but any PC would have worked fine. The PC is running the Linux operating system, in a configuration based on the Red Hat 4.0 distribution and customized slightly by the department's linux gurus. Control software was written almost exclusively in the Perl programming language version 5.0. A very small Perl Module loads in a bit of C code to directly read and write the parallel port. Programming all of the test cases in perl has been very successful; the high-level constructs built into the language and rapid prototyping possible due to its interpretive nature are significant advantages to this approach.
Other external equipment used in our test setup includes an HP 8656B signal generator for providing the chip clock (400 MHz) and a pile of power supplies.