This plot of the test chip has the receiver at the top and the transmitter at the bottom. Circuitry for the two functions is almost completely independent. The die measures 3.8x3mm, a size dictated mainly by the number of pads required.
The overall chip block diagram is shown above, along with some of the external connections required for operation. The transmitter/receiver pairs operate mesochronously. The transmitter section, shown on the left in this diagram, accepts data from one of three sources: a ROM, which alternately sends the two 10-bit sequences 0101010100 and 1010101011 used to initialize the receiver's data framer; a RAM, which can be loaded with 8 words of any desired 10-bit data; and a linear-feedback shift register which produces a (2^20 - 1)-bit pseudorandom sequence. The data source for the transmitter, the contents of the pattern RAM, and the strength coefficients for the filters are loaded into registers in the transmitter using a serial scan path.
The transmitter is realized using 400 MHz circuitry. A 10-phase clock sequences 10 data bits from 10 current-steering DACs, whose output strength is determined by the filter, based on the values of 5 successive bits of data.
The analog sampler is essentially a clocked sense amplifier whose two inputs are the signal to be sampled and a reference voltage generated off-chip and brought onto the chip through only an ESD protection network. The reference voltage is low-pass filtered at each sampler with a long poly resistor and a MOS capacitor. The NMOS cap shown in the figure is replaced by a PMOS cap for sampled signals that are referenced to Vdd. The sampler is triggered by an off-chip sampling clock, generated at PECL levels and distributed differentially on-chip. Each sampler has a differential buffer amplifier that converts the PECL input clock levels to full-swing CMOS signals. The sampler is quite compact, occupying only about 90x180 lambda. Layout was done very carefully to balance capacitance on the two arms of the sense amp. Even with perfect transistor matching, it appears that offsets due to unbalanced charge injection amount to a few 10s of millivolts. We estimate the aperture of the sampler to be a few 10s of picoseconds, but plan to measure it on another test chip now in fabrication.