William J. Dally
University of North Carolina at Chapel Hill
Results of an experimental 0.5-micron CMOS, 4-Gbps signaling chip show the effectiveness of a simple transition-filter equalization technique. The chip uses a tracking clock recovery receiver, in which a 21-phase clock is servoed to center every other clock on the center of the data "eye."
Keywords: High-speed signaling, clock recovery, equalization, interconnections
Vol. 18, No. 1,
Copyright (c) 1998 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.