A Tracking Clock Recovery Receiver for 4-Gbps Signaling

John Poulton
University of North Carolina at Chapel Hill

William J. Dally
Stanford University

Steve Tell
University of North Carolina at Chapel Hill

Results of an experimental 0.5-micron CMOS, 4-Gbps signaling chip show the effectiveness of a simple transition-filter equalization technique. The chip uses a tracking clock recovery receiver, in which a 21-phase clock is servoed to center every other clock on the center of the data "eye."

Keywords: High-speed signaling, clock recovery, equalization, interconnections

IEEE Micro, Vol. 18, No. 1, January/February 1998
Copyright (c) 1998 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.



Last modified: Wed Jul 15 10:30:44 EDT 1998 by
Steve Tell