William J. Dally
Stanford University
Steve Tell
University of North Carolina at Chapel Hill
Results of an experimental 0.5-micron CMOS, 4-Gbps signaling chip show the effectiveness of a simple transition-filter equalization technique. The chip uses a tracking clock recovery receiver, in which a 21-phase clock is servoed to center every other clock on the center of the data "eye."
Keywords: High-speed signaling, clock recovery, equalization, interconnections
IEEE Micro,
Vol. 18, No. 1,
January/February 1998
Copyright (c) 1998 Institute of
Electrical and Electronics Engineers, Inc. All rights
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