John Poulton

Gary Bishop

Office:  SN255

Office:  SN245

Phone:  2-1743

Phone:  2-1886

email:  jp@cs.unc.edu

email:  gb@cs.unc.edu

Steve Tell

Office:  SN259

Phone:  2-1845

email:  tell@cs.unc.edu


Lecture 1 Introduction & Outline January 13, 1998
Lecture 2 Process and Tools Overview January 15, 1998
Lecture 3 Magic Layout Intro, Elementary Gates January 20, 1998
Lecture 4 Heirarchy; Simulation Intro January 22, 1998
Lecture 5 Adders, Layout Techniques January 27, 1998
Lecture 6 Control Structures; Sequential Machines January 29, 1998
Lecture 7 All About MOSFETS February 3, 1998
Lecture 8 FET Parasitics February 10, 1998
Lecture 9 Fet Characteristics -> Circuit Behavior February 12, 1998
Lecture 10 Tau Model, Buffer Chains February 17, 1998
Lecture 11 IRSIM techniques February 24, 1998
Lecture 12 Power, Margins, Noise February 26, 1998
Lecture 13 Other Logic Styles March 3, 1998
Lecture 14 Clocking March 17, 1998
Lec. 14 Addendum The SECS electrical rule checker March 17, 1998
Lecture 15 Latches March 19, 1998
Lecture 16 Flip Flops, Failure Mechanisms March 24, 1998
Lecture 17 Guest Lecture: Corporate IC Design March 26, 1998
Lecture 18 Memory Cells March 31, 1998
Lecture 19 More on SRAMs April 2, 1998
Lecture 20 The Verilog Hardware Description Language April 7, 1998
Lecture 21 Analog CMOS April 9, 1998
Lecture 22 Adders Revisited April 14, 1998
Lecture 23 Guest Lecture: Metastability April 21, 1998
Lecture 24 I/O pads, ESD, High Speed Signaling April 23, 1998


Magic Cheat Sheet