FastLinks is a project to develop solutions to fundamental limits on the speed of chip-to-chip interconnect. Work begun in 1996 has produced an experimental 0.5m CMOS chip to test transmitter equalization (to eliminate intersymbol interference from frequency-dependent attenuation due to skin effect) and tracking clock recovery (to servo the receiver sampling clock to the data stream). The chip supports a differential data link at 4Gbits/sec over several meters of lossy interconnect. Tests were performed during summer 1997; both the equalization approach and the tracking clock recovery receiver worked as expected. A new 4Gb/s chip is in fabrication as of Spring, 1998, and designs are underway for a 1-2Gb/s equalized, edge-rate controlled, LVDS-compliant transceiver. Responsibilities: Principal Investigator, in collaboration with Prof. William J. Dally (Computer Systems Laboratory, Stanford University) and Steve Tell (UNC-CS).
PixelFlow, an object-parallel graphics system based on the concept of image composition. Machine consists of a number of identical board-level hardware units, each essentially a complete graphics system, interconnected by a very high-speed image-oriented linear network (~100 Gbits/second). PixelFlow is uniquely scalable, from compact single-board systems to very large systems, and is capable of performance perhaps as high as 100M shaded, texture, anti-aliased polygons per second. The machine also features highly parallel interconnect to a host machine; for large PixelFlow configurations, we anticipate that the host will be a parallel supercomputer--this combination of supercomputing and super-graphics will allow unprecedented performance for interactive scientific visualization, immersive virtual worlds experiments, and a variety of other applications. As of summer 1998, two prototype machines are running and supporting application development at HP's Fort Collins facility and at UNC. Responsibilities: Principal Investigator (with H. Fuchs); member of hardware designer team (with S. Molnar and J. Eyles) for custom chips, boards. Other commercial versions of PixelFlow under development by patent licensees IDT (RTP, NC) and PixelFusion (Bristol, UK).
PixelFlow Pad Library, a collection of I/O structures used in our most recent graphics system. The library consists of web-accessible documentation, magic layouts, and our in-house magic technology files. I/O cells include both conventional and high-performance current-mode signaling circuits, DLL clock aligners, a JTAG controller, and various other functions. All have been fabricated on Hewlett-Packard's CMOS14, a 3-metal 0.5 micron CMOS process accessible through the MOSIS service, and all have been tested on working silicon. Pad protection structures conform to HP's Class 2 (2kV) requirements and have been ESD tested at or above this level.
Pixel-Planes 5, a heterogeneous multicomputer for interactive 3D graphics. Features: Data base traversal and geometric processing on MIMD parallel array of Intel i860-based processors. Image-oriented processing on multiple 128x128 SIMD computing surfaces, built using custom, logic-enhanced memory chips that perform most pixel-oriented computations in parallel at each pixel; chips implement a novel unified mathematical formulation for these computations in terms of linear (and quadratic) expressions evaluated in parallel on the screen space. Processors, frame buffer, host interface all interconnected on 5Gb/sec 100K ECL-based token ring network. Performance: >2M Phong-shaded polygons/second, interactive volume rendering, interactive radiosity computation. Responsibilities: Principal Investigator (1987-present); principal author of proposals leading to this, and previous, project funding ($9M over nine years). Prototype machine completed, summer 1990; in regular production use since then in UNC-CS's Graphics and Imaging Laboratory; demonstrated at SIGGRAPH '91 "Virtual Worlds" gallery. Commercial graphics systems, based on Pixel-Planes 5 custom chips, began shipping from both Division and Ivex Corp during 1994. Pixel-Planes 5 was retired from service at UNC in September 1997.
Pixel-planes 4, first full-scale prototype graphics system built with the custom, logic-enhanced memory chips like those described above. A single 512x512 computing surface implemented in 2,048 custom 3-µ nMOS chips (63K transistors, 10MHz). The system rendered over 35,000 Gouraud-shaded, z-buffered triangles per second and executed a wide variety of other graphics and image-processing algorithms. Completed in August, 1986 and demonstrated at SIGGRAPH '86, it was one of the fastest systems at that date, and it remained in regular, daily use in the UNC-CS Graphics Laboratory until December 1991. Responsibilities: Co-PI (1981-87); one of two principal system architects (with Henry Fuchs); one of two custom chip designers (with John Eyles); Project Manager.
MUsIC (Medical Ultrasound Imaging Chip) contains most signal processing elements for a phased array ultrasound imager. Many chips can be combined to process data from a real-time 3D volume imaging system; applications include cardiovascular and obstetrical diagnosis. Developed in collaboration with Olaf von Ramm, Duke Biomedical Engineering Department, and Volumetric Medical Imaging, Inc., Durham, NC. Previous-generation chip (MUsIC 2.0) contains 125K devices in 2µ CMOS at 30MHz data rates; correct, full-speed operation on first silicon, summer 1989; board-level prototype of 3D imaging system based on MUsIC 2.0 completed summer 1991. MUsIC 3.2, a 40MHz 1.2µ chip completed in 1994, was the basis for the beam-former in the world's first electronically steered 3D ultrasound imager, now available in commercial form from Volumetric Medical Imaging, Inc., Durham, NC, which shipped its first machines in September 1997. A more recent version of this chip, MUsIC 4.0, is currently shipping in these machines. It is implemented in a 0.5µ 2-metal CMOS process and contains 150K of SRAM and 4 10-bit video DACs. Responsibilities: PI, managing one ASIC designer; chip logic and layout designer.