Some Links The only useful Free (Open Source) verilog simulator+synthesizer I know of. Slides from John Poulton's COMP 268, spring 1998. Helpful may be the verilog lecture: The site of John Cooley, EDA pundit. Nominally a Synopsis user's group site it has a lot of low-level tool-specific discussion, but there's also a bunch of good general information there. Contains some logic style, and also a lot of detail about how the simulator and its notion of time works. A general introduction, plus some detailed examples. Links section includes a detailed example problem specification - UART plus a suggested solution. On-line Verilog HDL Quick Reference Guide by Stuart Sutherland of Sutherland HDL, Inc. - Portland, Oregon, USA Verilog mode for emacs, Verilog FAQ, and other links.x Emacs-Wiki.el, the tool I used to format these notes.