http://icarus.com/eda/verilog/ The only useful Free (Open Source) verilog simulator+synthesizer I know of.
http://www.cs.unc.edu/~jp/comp268/VLSI-Slides/ Slides from John Poulton's COMP 268, spring 1998. Helpful may be the verilog lecture: http://www.cs.unc.edu/~jp/comp268/VLSI-Slides/Lecture20/slide01.html
http://www.deepchip.com The site of John Cooley, EDA pundit. Nominally a Synopsis user's group site it has a lot of low-level tool-specific discussion, but there's also a bunch of good general information there.
http://www.ece.cmu.edu/~thomas/VSLIDES.pdf Contains some logic style, and also a lot of detail about how the simulator and its notion of time works.
http://www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/index.html A general introduction, plus some detailed examples. Links section includes a detailed example problem specification - UART plus a suggested solution.
http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html On-line Verilog HDL Quick Reference Guide by Stuart Sutherland of Sutherland HDL, Inc. - Portland, Oregon, USA
http://www.verilog.com Verilog mode for emacs, Verilog FAQ, and other links.x
http://repose.cx/emacs/wiki/ Emacs-Wiki.el, the tool I used to format these notes.