module cntr32(clk, res, out);

    input clk;

    input res;

    output out;

      reg [31:0] count;

      always @ (posedge res or posedge clk)

          if(res)

                count <= 0;

           else

                count <= count + 1;

       assign out = count[22]; // Could use parameter

endmodule

module button_test(clk, btn, q);

     input clk;

     input btn;

     output q;

     reg q;

     always @ (posedge clk)

     begin

           if(btn == 1)

                q <= 1;

           else

                q <= 0;

     end

endmodule

module led_on(clk, button, s6);

     input clk;

     input button;

     output s6;

     wire clkb;

     cntr32 C1(clk, 0, clkb);

     button_test B1(clkb, ~button, s6);

endmodule

=================================

module seq_rec_v(CLK, RESET, X, Z);

     input CLK, RESET, X;

     output Z;

     reg [1:0] state, next_state;

     reg Z;

     parameter A = 2'b00, B = 2'b01, C = 2 'b10, D = 2'b11;

always @(X or state)

     begin

           case (state)

             A: if (X == 1)

                 next_state <= B;

                else

                 next_state <= A;

             B: if(X) next_state <= C;else next_state <= A;

             C: if(X) next_state <= C;else next_state <= D;

             D: if(X) next_state <= B;else next_state <= A;

           endcase

  end

always @(posedge CLK or posedge RESET)

begin

     if (RESET == 1)

           state <= A;

     else

           state <= next_state;

end

always @(X or state)

begin

     case(state)

           A: Z <= 0;

           B: Z <= 0;

           C: Z <= 0;

           D: Z <= X ? 1 : 0;

endcase

end

endmodule