1/16 -- Lab 1, Using the Xilinx tools to design with a schematic diagram
1/23 -- Lab 2, Combinational logic in Verilog, ModelSim simulator
1/30 -- Lab 3, Design an adder and test using Verilog code
2/6 -- Lab 4, Design a digital lock
2/13 -- Lab 5, Design a VGA timing generator
2/20 and 2/27 -- Labs 6 and 7, Finish the VGA terminal
3/5 -- Lab 8, the MIPS datapath
3/19 -- Lab 9, add the lw sw instructions. Instead of a report, just send a copy of your working code.
3/26 -- Lab 10, add branching. This completes the basic MIPS computer. Send a copy of your working code.
4/2 -- Lab 11, add the peripherals: your VGA terminal and a keyboard. Here's my keyboard code for you to use. You'll want to memory map the register that holds the received character. Send a copy of your working code.
4/9 -- holiday
4/16 -- Work on your demo. No report.
4/23 -- Demo. Send a final report describing your design and problems along the way, along with a copy of your working code.