`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// Montek Singh
// 11/13/2014 
//
// This is a self-checking tester for your full MIPS processor 
// (Lab 10 and Project).  Use the 2nd test program provided under Lab 10,
// i.e., initialize instruction memory with test2.txt, and data memory
// with test2_data.txt.
//
// Use this tester carefully!  The names of your top-level input/output
// and internal signals may be different, so modify all of signal names on the
// right-hand-side of the "wire" assigments appearing above the uut
// instantiation.  Observe that the uut itself only has clock and reset inputs
// now, and no debug outputs.  Instead, the internal signals are "pulled out"
// using the member selection, or dot, operator (".").
//
//////////////////////////////////////////////////////////////////////////////////


module mips_test;

   // Inputs
   reg clk;
   reg reset;


// *****************************************************************
// CHANGE the names on the right-hand-side of these assignments to
// match the names of instances and signals actually used in your
// design.
// *****************************************************************

   // Signals inside top-level module uut
   wire [31:0] pc             =uut.pc;                      // PC
   wire [31:0] instr          =uut.instr;                   // instr coming out of instr mem
   wire [31:0] dmem_addr      =uut.dmem_addr;               // addr sent to data mem
   wire        dmem_write     =uut.dmem_write;              // write enable for data mem
   wire [31:0] dmem_readdata  =uut.dmem_readdata;           // data read from data mem
   wire [31:0] dmem_writedata =uut.dmem_writedata;          // write data for data mem

   // Signals inside module uut.mips
   wire        regwrite       =uut.mips.regwrite;           // WERF = write enable for register file
   wire  [4:0] ALUFN          =uut.mips.ALUFN;              // ALU function
   wire        flagZ          =uut.mips.flagZ;              // Zero flag

   // Signals inside module uut.mips.dp (datapath)
   wire [31:0] ReadData1      =uut.mips.dp.ReadData1;       // Reg[rs]
   wire [31:0] ReadData2      =uut.mips.dp.ReadData2;       // Reg[rt]
   wire [31:0] alu_result     =uut.mips.dp.alu_result;      // ALU's output
   wire [4:0]  reg_writeaddr  =uut.mips.dp.reg_writeaddr;   // destination register
   wire [31:0] reg_writedata  =uut.mips.dp.reg_writedata;   // write data for register file
   wire [31:0] signImm        =uut.mips.dp.signImm;         // sign-/zero-extended immediate
   wire [31:0] aluA           =uut.mips.dp.aluA;            // operand A for ALU
   wire [31:0] aluB           =uut.mips.dp.aluB;            // operand B for ALU

// *****************************************************************
// END OF CHANGES
// You will likely not need to make any changes below.
// *****************************************************************



   // Instantiate the Unit Under Test (UUT)
   top uut (
      .clk(clk), 
      .reset(reset)
   );

   initial begin
      // Initialize Inputs
      clk = 0;
      reset = 0;
   end

   initial begin
      #0.5 clk = 0;
      forever
         #0.5 clk = ~clk;
   end
   
   initial begin
      #50 $finish;
   end
   
   
   
   // SELF-CHECKING CODE
   
   checker c();

   wire [31:0] c_pc=c.pc;
   wire [31:0] c_instr=c.instr;
   wire [31:0] c_dmem_addr=c.dmem_addr;
   wire        c_dmem_write=c.dmem_write;
   wire [31:0] c_dmem_readdata=c.dmem_readdata;
   wire [31:0] c_dmem_writedata=c.dmem_writedata;
   wire        c_regwrite=c.regwrite;
   wire  [4:0] c_ALUFN=c.ALUFN;
   wire        c_flagZ=c.flagZ;
   wire [31:0] c_ReadData1=c.ReadData1;
   wire [31:0] c_ReadData2=c.ReadData2;
   wire [31:0] c_alu_result=c.alu_result;
   wire [4:0]  c_reg_writeaddr=c.reg_writeaddr;
   wire [31:0] c_reg_writedata=c.reg_writedata;
   wire [31:0] c_signImm=c.signImm;
   wire [31:0] c_aluA=c.aluA;
   wire [31:0] c_aluB=c.aluB;
   
  
   function mismatch;  // some trickery needed to match two values with don't cares
      input p, q;      // mismatch in a bit position is ignored if q has an 'x' in that bit
      integer p, q;
      mismatch = (((p ^ q) ^ q) !== q);
   endfunction

   wire ERROR = ERROR_pc | ERROR_instr | ERROR_dmem_addr | ERROR_dmem_write | ERROR_dmem_readdata 
              | ERROR_dmem_writedata | ERROR_regwrite | ERROR_ALUFN | ERROR_flagZ
              | ERROR_ReadData1 | ERROR_ReadData2 | ERROR_alu_result | ERROR_reg_writeaddr
              | ERROR_reg_writedata | ERROR_signImm | ERROR_aluA | ERROR_aluB;
   
   wire ERROR_pc             = mismatch(pc, c.pc) ? 1'bx : 1'b0;
   wire ERROR_instr          = mismatch(instr, c.instr) ? 1'bx : 1'b0;
   wire ERROR_dmem_addr      = mismatch(dmem_addr, c.dmem_addr) ? 1'bx : 1'b0;
   wire ERROR_dmem_write     = mismatch(dmem_write, c.dmem_write) ? 1'bx : 1'b0;
   wire ERROR_dmem_readdata  = mismatch(dmem_readdata, c.dmem_readdata) ? 1'bx : 1'b0;
   wire ERROR_dmem_writedata = c.dmem_write & (mismatch(dmem_writedata, c.dmem_writedata) ? 1'bx : 1'b0);
   wire ERROR_regwrite       = mismatch(regwrite, c.regwrite) ? 1'bx : 1'b0;
   wire ERROR_ALUFN          = mismatch(ALUFN, c.ALUFN) ? 1'bx : 1'b0;
   wire ERROR_flagZ          = mismatch(flagZ, c.flagZ) ? 1'bx : 1'b0;
   wire ERROR_ReadData1      = mismatch(ReadData1, c.ReadData1) ? 1'bx : 1'b0;
   wire ERROR_ReadData2      = mismatch(ReadData2, c.ReadData2) ? 1'bx : 1'b0;
   wire ERROR_alu_result     = mismatch(alu_result, c.alu_result) ? 1'bx : 1'b0;
   wire ERROR_reg_writeaddr  = c.regwrite & (mismatch(reg_writeaddr, c.reg_writeaddr) ? 1'bx : 1'b0);
   wire ERROR_reg_writedata  = c.regwrite & (mismatch(reg_writedata, c.reg_writedata) ? 1'bx : 1'b0);
   wire ERROR_signImm        = mismatch(signImm, c.signImm) ? 1'bx : 1'b0;
   wire ERROR_aluA           = mismatch(aluA, c.aluA) ? 1'bx : 1'b0;
   wire ERROR_aluB           = mismatch(aluB, c.aluB) ? 1'bx : 1'b0;

   initial begin
      $monitor("#%5d {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h%h, 32'h%h, 32'h%h, 1'b%b, 32'h%h, 32'h%h, 1'b%b, 5'b%b, 1'b%b, 32'h%h, 32'h%h, 32'h%h, 5'h%h, 32'h%h, 32'h%h, 32'h%h, 32'h%h};",
               $time, pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB);
   end
      
endmodule



// CHECKER MODULE
module checker();

   reg  [31:0] pc;
   reg  [31:0] instr;
   reg  [31:0] dmem_addr;
   reg         dmem_write;
   reg  [31:0] dmem_readdata;
   reg  [31:0] dmem_writedata;
   reg         regwrite;
   reg   [4:0] ALUFN;
   reg         flagZ;
   reg  [31:0] ReadData1;
   reg  [31:0] ReadData2;
   reg  [31:0] alu_result;
   reg  [4:0]  reg_writeaddr;
   reg  [31:0] reg_writedata;
   reg  [31:0] signImm;
   reg  [31:0] aluA;
   reg  [31:0] aluB;


initial begin
fork
#0 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000000, 32'hac000000, 32'h00000000, 1'b1, 32'h00000000, 32'h00000000, 1'b0, 5'b0xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'hxx, 32'h0000000X, 32'h00000000, 32'h00000000, 32'h00000000};
#1 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000004, 32'hac000004, 32'h00000004, 1'b1, 32'h00000000, 32'h00000000, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000000, 32'h00000004, 5'hxx, 32'h0000000X, 32'h00000004, 32'h00000000, 32'h00000004};
#2 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000008, 32'h8c090004, 32'h00000004, 1'b0, 32'h00000000, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h00000004, 5'h09, 32'h00000000, 32'h00000004, 32'h00000000, 32'h00000004};
#3 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000000c, 32'h8c080000, 32'h00000000, 1'b0, 32'h00000000, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b1, 32'h00000000, 32'hxxxxxxxx, 32'h00000000, 5'h08, 32'h00000000, 32'h00000000, 32'h00000000, 32'h00000000};
#4 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000010, 32'h00095080, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'bx0010, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'h0a, 32'h00000000, 32'h00005080, 32'h00000002, 32'h00000000};
#5 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000014, 32'h8d4a0008, 32'h00000008, 1'b0, 32'h00000007, 32'h00000000, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000000, 32'h00000008, 5'h0a, 32'h00000007, 32'h00000008, 32'h00000000, 32'h00000008};
#6 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000018, 32'h010a4020, 32'h00000007, 1'b0, 32'h00000000, 32'h00000007, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000007, 32'h00000007, 5'h08, 32'h00000007, 32'h00004020, 32'h00000000, 32'h00000007};
#7 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000001c, 32'hac080000, 32'h00000000, 1'b1, 32'h00000000, 32'h00000007, 1'b0, 5'b0xx01, 1'b1, 32'h00000000, 32'h00000007, 32'h00000000, 5'hxx, 32'h000000X0, 32'h00000000, 32'h00000000, 32'h00000000};
#8 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000020, 32'h21290001, 32'h00000001, 1'b0, 32'h00000007, 32'h00000000, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000000, 32'h00000001, 5'h09, 32'h00000001, 32'h00000001, 32'h00000000, 32'h00000001};
#9 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000024, 32'hac090004, 32'h00000004, 1'b1, 32'h00000000, 32'h00000001, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000001, 32'h00000004, 5'hxx, 32'h000000XX, 32'h00000004, 32'h00000000, 32'h00000004};
#10 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000028, 32'h292a0005, 32'h00000001, 1'b0, 32'h00000007, 32'h00000007, 1'b1, 5'b1x011, 1'b0, 32'h00000001, 32'h00000007, 32'h00000001, 5'h0a, 32'h00000001, 32'h00000005, 32'h00000001, 32'h00000005};
#11 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000002c, 32'h1540fff8, 32'h00000001, 1'b0, 32'h00000007, 32'h00000000, 1'b0, 5'b1xx01, 1'b0, 32'h00000001, 32'h00000000, 32'h00000001, 5'hxx, 32'h000000XX, 32'hfffffff8, 32'h00000001, 32'h00000000};
#12 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000010, 32'h00095080, 32'h00000004, 1'b0, 32'h00000001, 32'h00000001, 1'b1, 5'bx0010, 1'b0, 32'h00000000, 32'h00000001, 32'h00000004, 5'h0a, 32'h00000004, 32'h00005080, 32'h00000002, 32'h00000001};
#13 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000014, 32'h8d4a0008, 32'h0000000c, 1'b0, 32'h00000008, 32'h00000004, 1'b1, 5'b0xx01, 1'b0, 32'h00000004, 32'h00000004, 32'h0000000c, 5'h0a, 32'h00000008, 32'h00000008, 32'h00000004, 32'h00000008};
#14 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000018, 32'h010a4020, 32'h0000000f, 1'b0, 32'h00000008, 32'h00000008, 1'b1, 5'b0xx01, 1'b0, 32'h00000007, 32'h00000008, 32'h0000000f, 5'h08, 32'h0000000f, 32'h00004020, 32'h00000007, 32'h00000008};
#15 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000001c, 32'hac080000, 32'h00000000, 1'b1, 32'h00000007, 32'h0000000f, 1'b0, 5'b0xx01, 1'b1, 32'h00000000, 32'h0000000f, 32'h00000000, 5'hxx, 32'h000000XX, 32'h00000000, 32'h00000000, 32'h00000000};
#16 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000020, 32'h21290001, 32'h00000002, 1'b0, 32'h0000000f, 32'h00000001, 1'b1, 5'b0xx01, 1'b0, 32'h00000001, 32'h00000001, 32'h00000002, 5'h09, 32'h00000002, 32'h00000001, 32'h00000001, 32'h00000001};
#17 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000024, 32'hac090004, 32'h00000004, 1'b1, 32'h00000001, 32'h00000002, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000002, 32'h00000004, 5'hxx, 32'h000000XX, 32'h00000004, 32'h00000000, 32'h00000004};
#18 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000028, 32'h292a0005, 32'h00000001, 1'b0, 32'h0000000f, 32'h00000008, 1'b1, 5'b1x011, 1'b0, 32'h00000002, 32'h00000008, 32'h00000001, 5'h0a, 32'h00000001, 32'h00000005, 32'h00000002, 32'h00000005};
#19 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000002c, 32'h1540fff8, 32'h00000001, 1'b0, 32'h0000000f, 32'h00000000, 1'b0, 5'b1xx01, 1'b0, 32'h00000001, 32'h00000000, 32'h00000001, 5'hxx, 32'h000000Xx, 32'hfffffff8, 32'h00000001, 32'h00000000};
#20 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000010, 32'h00095080, 32'h00000008, 1'b0, 32'h00000007, 32'h00000002, 1'b1, 5'bx0010, 1'b0, 32'h00000000, 32'h00000002, 32'h00000008, 5'h0a, 32'h00000008, 32'h00005080, 32'h00000002, 32'h00000002};
#21 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000014, 32'h8d4a0008, 32'h00000010, 1'b0, 32'h00000009, 32'h00000008, 1'b1, 5'b0xx01, 1'b0, 32'h00000008, 32'h00000008, 32'h00000010, 5'h0a, 32'h00000009, 32'h00000008, 32'h00000008, 32'h00000008};
#22 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000018, 32'h010a4020, 32'h00000018, 1'b0, 32'h00000008, 32'h00000009, 1'b1, 5'b0xx01, 1'b0, 32'h0000000f, 32'h00000009, 32'h00000018, 5'h08, 32'h00000018, 32'h00004020, 32'h0000000f, 32'h00000009};
#23 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000001c, 32'hac080000, 32'h00000000, 1'b1, 32'h0000000f, 32'h00000018, 1'b0, 5'b0xx01, 1'b1, 32'h00000000, 32'h00000018, 32'h00000000, 5'hxx, 32'h000000Xx, 32'h00000000, 32'h00000000, 32'h00000000};
#24 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000020, 32'h21290001, 32'h00000003, 1'b0, 32'h00000018, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000002, 32'h00000002, 32'h00000003, 5'h09, 32'h00000003, 32'h00000001, 32'h00000002, 32'h00000001};
#25 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000024, 32'hac090004, 32'h00000004, 1'b1, 32'h00000002, 32'h00000003, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000003, 32'h00000004, 5'hxx, 32'h000000XX, 32'h00000004, 32'h00000000, 32'h00000004};
#26 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000028, 32'h292a0005, 32'h00000001, 1'b0, 32'h00000018, 32'h00000009, 1'b1, 5'b1x011, 1'b0, 32'h00000003, 32'h00000009, 32'h00000001, 5'h0a, 32'h00000001, 32'h00000005, 32'h00000003, 32'h00000005};
#27 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000002c, 32'h1540fff8, 32'h00000001, 1'b0, 32'h00000018, 32'h00000000, 1'b0, 5'b1xx01, 1'b0, 32'h00000001, 32'h00000000, 32'h00000001, 5'hxx, 32'h000000XX, 32'hfffffff8, 32'h00000001, 32'h00000000};
#28 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000010, 32'h00095080, 32'h0000000c, 1'b0, 32'h00000008, 32'h00000003, 1'b1, 5'bx0010, 1'b0, 32'h00000000, 32'h00000003, 32'h0000000c, 5'h0a, 32'h0000000c, 32'h00005080, 32'h00000002, 32'h00000003};
#29 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000014, 32'h8d4a0008, 32'h00000014, 1'b0, 32'h0000000a, 32'h0000000c, 1'b1, 5'b0xx01, 1'b0, 32'h0000000c, 32'h0000000c, 32'h00000014, 5'h0a, 32'h0000000a, 32'h00000008, 32'h0000000c, 32'h00000008};
#30 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000018, 32'h010a4020, 32'h00000022, 1'b0, 32'hxxxxxxxx, 32'h0000000a, 1'b1, 5'b0xx01, 1'b0, 32'h00000018, 32'h0000000a, 32'h00000022, 5'h08, 32'h00000022, 32'h00004020, 32'h00000018, 32'h0000000a};
#31 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000001c, 32'hac080000, 32'h00000000, 1'b1, 32'h00000018, 32'h00000022, 1'b0, 5'b0xx01, 1'b1, 32'h00000000, 32'h00000022, 32'h00000000, 5'hxx, 32'h000000XX, 32'h00000000, 32'h00000000, 32'h00000000};
#32 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000020, 32'h21290001, 32'h00000004, 1'b0, 32'h00000003, 32'h00000003, 1'b1, 5'b0xx01, 1'b0, 32'h00000003, 32'h00000003, 32'h00000004, 5'h09, 32'h00000004, 32'h00000001, 32'h00000003, 32'h00000001};
#33 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000024, 32'hac090004, 32'h00000004, 1'b1, 32'h00000003, 32'h00000004, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000004, 32'h00000004, 5'hxx, 32'h000000Xx, 32'h00000004, 32'h00000000, 32'h00000004};
#34 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000028, 32'h292a0005, 32'h00000001, 1'b0, 32'h00000022, 32'h0000000a, 1'b1, 5'b1x011, 1'b0, 32'h00000004, 32'h0000000a, 32'h00000001, 5'h0a, 32'h00000001, 32'h00000005, 32'h00000004, 32'h00000005};
#35 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000002c, 32'h1540fff8, 32'h00000001, 1'b0, 32'h00000022, 32'h00000000, 1'b0, 5'b1xx01, 1'b0, 32'h00000001, 32'h00000000, 32'h00000001, 5'hxx, 32'h000000XX, 32'hfffffff8, 32'h00000001, 32'h00000000};
#36 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000010, 32'h00095080, 32'h00000010, 1'b0, 32'h00000009, 32'h00000004, 1'b1, 5'bx0010, 1'b0, 32'h00000000, 32'h00000004, 32'h00000010, 5'h0a, 32'h00000010, 32'h00005080, 32'h00000002, 32'h00000004};
#37 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000014, 32'h8d4a0008, 32'h00000018, 1'b0, 32'h00000008, 32'h00000010, 1'b1, 5'b0xx01, 1'b0, 32'h00000010, 32'h00000010, 32'h00000018, 5'h0a, 32'h00000008, 32'h00000008, 32'h00000010, 32'h00000008};
#38 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000018, 32'h010a4020, 32'h0000002a, 1'b0, 32'hxxxxxxxx, 32'h00000008, 1'b1, 5'b0xx01, 1'b0, 32'h00000022, 32'h00000008, 32'h0000002a, 5'h08, 32'h0000002a, 32'h00004020, 32'h00000022, 32'h00000008};
#39 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000001c, 32'hac080000, 32'h00000000, 1'b1, 32'h00000022, 32'h0000002a, 1'b0, 5'b0xx01, 1'b1, 32'h00000000, 32'h0000002a, 32'h00000000, 5'hxx, 32'h000000XX, 32'h00000000, 32'h00000000, 32'h00000000};
#40 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000020, 32'h21290001, 32'h00000005, 1'b0, 32'h00000004, 32'h00000004, 1'b1, 5'b0xx01, 1'b0, 32'h00000004, 32'h00000004, 32'h00000005, 5'h09, 32'h00000005, 32'h00000001, 32'h00000004, 32'h00000001};
#41 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000024, 32'hac090004, 32'h00000004, 1'b1, 32'h00000004, 32'h00000005, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000005, 32'h00000004, 5'hxx, 32'h000000XX, 32'h00000004, 32'h00000000, 32'h00000004};
#42 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000028, 32'h292a0005, 32'h00000000, 1'b0, 32'h0000002a, 32'h00000008, 1'b1, 5'b1x011, 1'b1, 32'h00000005, 32'h00000008, 32'h00000000, 5'h0a, 32'h00000000, 32'h00000005, 32'h00000005, 32'h00000005};
#43 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h0000002c, 32'h1540fff8, 32'h00000000, 1'b0, 32'h0000002a, 32'h00000000, 1'b0, 5'b1xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'hxx, 32'h000000XX, 32'hfffffff8, 32'h00000000, 32'h00000000};
#44 {pc, instr, dmem_addr, dmem_write, dmem_readdata, dmem_writedata, regwrite, ALUFN, flagZ, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB} <= {32'h00000030, 32'h0800000c, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h0000000c, 32'h00000000, 32'h0000000X};
join
end

endmodule