`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:      Montek Singh
//
// Create Date:   23:17:22 8/25/2014
// Design Name:   add_sub_8bit
// Module Name:   D:/Comp541/Lab2/Lab2_test.v
// Project Name:  Lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: add_sub_8bit
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Lab2_test;

	// Inputs
	reg [7:0] A;
	reg [7:0] B;
	reg Subtract;

	// Outputs
	wire [7:0] Result;

	// Instantiate the Unit Under Test (UUT)
	add_sub_8bit uut (
		.A(A), 
		.B(B), 
		.Subtract(Subtract), 
		.Result(Result)
	);

	integer i;

	initial begin
		// Initialize Inputs
		A = 0;
		B = 0;
		Subtract = 0;

		// Wait 5 ns for global reset to finish
		#5;
        
		// Let us try some additions
		for(i=0; i<4; i=i+1)
		begin
		  #1 A = A + 11; B = B + 15;
		end
		  
		// Let us try some subtractions
		#5 Subtract = 1; A = 50; B = 10;
		for(i=0; i<4; i=i+1)
		begin
			#1 A = A - 10; B = B + 10;
		end
		
		#5 $finish;
	end
	
	initial begin
		// define time to be displayed in ns, with 2 decimals, and a width of 10 characters
		$timeformat(-9, 2, " ns", 10);
		$monitor("At time %t:  A=%d, B=%d, Subtract=%b, ToBornottoB=%b, Result=%d (%b)", 
					$time, A, B, Subtract, uut.ToBornottoB, Result, Result);
	end
	
endmodule