`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:49:42 02/01/2012
// Design Name:   CounterMod7Reset
// Module Name:   D:/Comp541/Lab3/CounterMod7Reset_test.v
// Project Name:  Lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: CounterMod7Reset
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module CounterMod7Reset_test;

	// Inputs
	reg clock;
	reg reset;
	reg Stop;

	// Outputs
	wire [2:0] value;

	// Instantiate the Unit Under Test (UUT)
	CounterMod7Reset uut (
		.clock(clock), 
		.reset(reset), 
		.Stop(Stop), 
		.value(value)
	);

	integer i;

	initial begin
		
		// Initialize Inputs
		clock = 0;
		reset = 0;

		// Wait 2 ns and then reset the counter
		#1 reset = 1;
		#1 clock = 1;
		#1 reset = 0; clock = 0; 
      
		// Let us count for 8 clock cycles
		// Each clock cycle is 2ns (1ns high and 1ns low)
		for(i=0; i<8; i=i+1) begin
		  #1 clock = ~clock;
		  #1 clock = ~clock;
		end
		
		// Wait 2 ns and then reset the counter
		#1 reset = 1;
		#1 clock = 1;
		#1 reset = 0; clock = 0; 

		// Let us count again 2 clock cycles
		for(i=0; i<2; i=i+1) begin
		  #1 clock = ~clock;
		  #1 clock = ~clock;
		end
		
		#2 $finish;
		
	end

	initial begin
		Stop = 0;
		# 15 Stop = 1;
		# 4 Stop = 0;
	end
	
endmodule