`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   09/09/2014
// Design Name:   vgatimer
// Module Name:   D:/Comp541/Lab4/vgatimer_test.v
// Project Name:  Lab4
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: vgatimer
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module xycounter_test;

   // Inputs
   reg clk;
   reg on;

   // Outputs
   wire [1:0] x;
   wire [1:0] y;
   

   // Uncomment the following line and change the parameters.
   // Be sure to change the bit widths of x and y above accordingly.
   //xycounter #(5, 3) uut (
   
   xycounter uut (
      .clk(clk), 
      .on(on),
      .x(x), 
      .y(y)
   );

   initial begin
      // 100 MHz clock ==> 10 ns period
      clk = 0;
      #10 clk = 1;
           
      forever
         #5 clk = ~clk;
   end

   initial begin
      #300 $finish;
   end

   initial begin
      on = 1;
      #52 on = 0;
      #30 on = 1;
   end
         
endmodule