`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Montek Singh
// 
// Create Date:    10/6/2014 
//////////////////////////////////////////////////////////////////////////////////

module vgadisplaydriver_test;

   // Inputs
   reg clk;

   // Outputs 			// Uncomment the lines that match your board
   wire [2:0] red; 		// Nexys 3
   wire [2:0] green; 	// Nexys 3
   wire [2:1] blue; 		// Nexys 3
   // wire [3:0] red; 		// Nexys 4
   // wire [3:0] green; 	// Nexys 4
   // wire [3:0] blue; 		// Nexys 4
   wire hsync;
   wire vsync;
 

   // Instantiate the Unit Under Test (UUT)
   vgadisplaydriver uut (
      .clk(clk), 
      .red(red), 
      .green(green), 
      .blue(blue), 
      .hsync(hsync), 
      .vsync(vsync)
   );

   initial begin
      // Initialize Inputs
      clk = 0;
      #10 clk = 1;

      forever
         #5 clk = ~clk;

   end
   
   initial begin
      #6000 $finish;   // should be long enough for one entire frame
   end

   
   checker c(checker_hsync, checker_vsync);
   wire ERROR_hsync = (hsync != checker_hsync)? 1'bX : 1'b0;
   wire ERROR_vsync = (vsync != checker_vsync)? 1'bX : 1'b0;


endmodule


module checker(
   output checker_hsync,
   output checker_vsync
   );
   
   assign checker_hsync = hsync;
   assign checker_vsync = vsync;
   
   reg hsync, vsync;

   initial begin
      fork
         #0000 {hsync, vsync} <= 2'b11;
         #0440 {hsync, vsync} <= 2'b01;
         #0560 {hsync, vsync} <= 2'b11;
         #1080 {hsync, vsync} <= 2'b01;
         #1200 {hsync, vsync} <= 2'b11;
         #1720 {hsync, vsync} <= 2'b01;
         #1840 {hsync, vsync} <= 2'b11;
         #2360 {hsync, vsync} <= 2'b01;
         #2480 {hsync, vsync} <= 2'b11;
         #3000 {hsync, vsync} <= 2'b01;
         #3120 {hsync, vsync} <= 2'b11;
         #3200 {hsync, vsync} <= 2'b10;
         #3640 {hsync, vsync} <= 2'b00;
         #3760 {hsync, vsync} <= 2'b10;
         #4280 {hsync, vsync} <= 2'b00;
         #4400 {hsync, vsync} <= 2'b10;
         #4480 {hsync, vsync} <= 2'b11;
         #4920 {hsync, vsync} <= 2'b01;
         #5040 {hsync, vsync} <= 2'b11;
         #5560 {hsync, vsync} <= 2'b01;
         #5680 {hsync, vsync} <= 2'b11;
      join
   end
endmodule