`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// Montek Singh
// 11/15/2014 
//
//////////////////////////////////////////////////////////////////////////////////

module top(input clk, input reset);

   wire [31:0] pc, instr, dmem_readdata, dmem_writedata, dmem_addr;
   wire dmem_write;

   // Uncomment *only* one of the following three lines:
   //    when simulating, get rid of the clock divider, and use the third line
   //    when synthesizing, use either the first or the second line, depending on your board
   //
   //clockdivider_Nexys3 clkdv(clk, clk100, clk50, clk25, clk12);
   //clockdivider_Nexys4 clkdv(clk, clk100, clk50, clk25, clk12);
   assign clk100=clk; assign clk50=clk; assign clk25=clk; assign clk12=clk;

   // For synthesis:  use an appropriate clock frequency(ies) below
   //   clk100 will work for only the most efficient designs
   //   clk50 or clk 25 should work for the vast majority
   //   the slowest designs will need clk12
   //
   // Use the same clock frequency for the MIPS and data memory/memIO modules
   // The displaydriver should keep the 100 MHz clock
   //
   mips mips(clk50, ...);
   imem imem(pc[31:0], instr);
   memIO memIO(clk50, ...);
   displayunit displayunit(clk100, ...);

endmodule