COMP 290 - Spring 2003

 

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COMP 290-084:  Clockless Logic

Spring 2003

Tues. and Thurs., 3:20-4:35pm, SN325

 

Introduction  [ppt slides]

Petri Nets [ppt slides] [pdf paper]

Logic Synthesis from Petri net specifications ("Petrify") [ps slides]

Hazard-Free 2-Level Logic Minimization (basics) [ppt slides]

Implicit Hazard-Free 2-Level Logic Minimization ("Impymin") [ppt slides] [pdf paper]

Asynchronous State Machine Synthesis

bulletPreliminary approach ("UCLOCK") [ppt slides] [ps paper]
bulletRefined approach ("CHASM" + "OPTIMISTA") [pdf slides] [ps slides] [pdf paper]

CAD Packages

bulletMINIMALIST
bulletTutorial [ppt slides]
bulletQuick demo [ps]
bulletPetrify
bulletTutorial [ps slides] [ps paper]

Mini-project:  Control synthesis

bulletProblem statement [pdf]
bulletCAD tool instructions

Review:  Logic Implementation Styles [ppt slides]

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Static Logic

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Dynamic Logic

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Transmission-Gate Logic

Asynchronous Pipeline Approaches:  Static Logic

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 MOUSETRAP [ppt slides] [ps paper]

Asynchronous Pipeline Approaches:  Dynamic Logic

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Williams PS0 pipeline style [ppt slides] [pdf paper]

Asynchronous Pipeline Approaches:  Dynamic Logic (contd.)

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Lookahead Pipelines [ppt slides] [pdf paper]

Asynchronous Pipeline Approaches:  Dynamic Logic (contd.)

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High-Capacity Pipelines [ppt slides] [pdf paper1] [pdf paper2]

Case Studies:

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High-speed adder for DSP applications [ppt slides] [pdf paper1]

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FIR filter chip with IBM [ppt slides] [pdf paper]

Performance Analysis:  FIFO's and Self-Timed Rings