September 9, 1997 Steve Tell tell@cs.unc.edu The MSL extractor is derived from the one in magic 6.3, with several enhancements. The main enhancement is to the handling of sidewall overlap capacitance. In addition to simple shielding of sideoverlap capacitance like that handled by the extractor in 6.5, we handle some additional related effects as described below. A previous version of the MSL extractor originated the notion of using floating point for capacitance values. Stefanos Sidropolos added this feature to the 6.5 extractor, and I've since brought the MSL extractor into line with his implementation. This provides two benefits: (1) Very large cumulative capacitances can be extracted, for example the Vdd-GND capacitance on a whole chip. (2) The numbers for capactance per square lambda and capacitance per lambda in the tech file can be specifed to greater than one femtofarad of precision. In modern submicron processes, these values are often in the range of 1-10 fF. The MSL extractor had another means for dealing with very small capacitance values. A keyword "cunit" specified a value by which to devide all capacitances by when printing them to the .ext file. Typical usage was to say "cunit 100" and then specify all capacitances in units of hundredths of femtofarads per unit. This feature is superseded by the use of floating point, but is still present because that was easier than ripping it out. Other features in the 6.5 extractor that are not in the MSL extractor: The planeorder and noplaneordering statements for specifying the order of the planes for handling some of the shielding cases. The MSL extractor parses thes lines for compatibility with tech files intended for the 6.5 extractor, but ignores the information. - The mapping of negative coordinates into nodenames for unnamed nodes was changed in 6.5. - the exts_subsTransistorTypes[] array in the exts_style structure is neither computed nor used. (I'm not sure what this is for) - Both the MSL extractor and 6.5 do the sorting of transistor terminals such that source and drain attributes on the right terminal, but the implementation is somewhat different. - The MSL extractor doesn't have a few debugging statements enabled with the CAP_DEBUG #define; these mostly relate to 6.5.1's independent implementation of sideoverlap shielding. ***************************************************************************** Installing the MSL extractor in magic 6.5.1 Unpack this tarfile in the magic-6.5.1 source directory. It will create a directory called extractmsl. Rename the extract directory to extractstd Create a symbolic link from extract to estractmsl: ln -s extractmsl extract (re)build magic as usual by running make. If you have already built magic, and want to switch between extractstd and extractmsl without doing a make clean and then recompling everything, try removing these files only: lib/extract.o include/extDebugInt.h include/extract.h include/extractInt.h ***************************************************************************** Details on enhanced sideoverlap capacitance handling in the MSL extractor: The syntax for the sideoverlap statement in the extract section of the tech file is the following (all on one line, but broken here for readability): sideoverlap intypes outtypes ovtypes capacitance [ovshieldtypes [ov2types [ov2capacitance [ov2shieldtypes]]]] The required arguments are the same as those handled by the 6.3 extractor. The first optional argument, ovshieldtypes, is the same as that handled by the 6.5 extractor, and specifies a list of layers that can occur in between the intypes and outtypes layers and shield the capacitance. The next several figures will illustrate the use of the additional parameters. Most basic case of sideoverlap: m1 ----------------- substrate ############################################### The original form of the sideoverlap statement would handles this case completely: sideoverlap allMetal1 space space/well 60 ***************************************************************************** Simple shielding: m1 ----------------- poly ------------------------- substrate ############################################### The presence of the poly layer between m1 and substrate prevents there from being any capacitance from m1 to ground. Both the MSL extractor and the 6.5 extractor describe this case with the following sort of line. sideoverlap allMetal1 space space/well 60 allActive,allPoly ***************************************************************************** Capacitance sharing: m2 --------------------------- m1 ----------------- substrate ############################################### In this case, the capacitance from m1 to ground due to sidewall effects is reduced by the presence of the metal 2 layer above it. Some of the field lines from the side of the metal 1 layer are diverted to the metal 2 layer. The MSL extractor describes this with a pair of sideoverlap lines like this. The ov2capacitance values are almost always negative. sideoverlap allMetal1 space space/well 60 allActive,allPoly sideoverlap allMetal1 space space/well 0 allActive,allPoly m2,m3c/m2 -26 The capacitance values in this example are made up, but in at least one real process, the sideoverlap m1-substrate capacitance really is reduced by almost half. Since sideoverlap capacitance is a significant part of the total in fine-line processes, this can make a significant difference. ***************************************************************************** Shielded capacitance sharing: m3 --------------------------- m2 ----------------------------------- m1 ----------------- substrate ############################################### There would normally be capacitance sharing from the sidewall of the m1 layer to the m3 layer, but the m2 layer shields this effect. This is described by a line like this: sideoverlap allMetal1 space space/well 0 allActive,allPoly m3 -20 m2,m2c/m2 To completely describe the sideoverlap capacitances and all of the shielding effects requires a lot of sideoverlap lines in the tech file. The numbers for use in these lines need to be computed from detailed tables of interlayer capacitances supplied by your fab vendor. This information is almost always available only under a nondisclosure agreement of some kind. I don't know if such information is available from MOSIS in any form. Here is an example of the sideoverlap lines for metal1 only in a hypothetical 3-metal CMOS process. Additional lines are required for metal2 and metal3. The capacitance numbers are fictitious, although their relative values are representative of some real processes. sideoverlap allMetal1 space space/well 60 allActive,allPoly sideoverlap allMetal1 space space/well 0 allActive,allPoly m2,m3c/m2 -28 sideoverlap allMetal1 space space/well 0 allActive,allPoly m3 -25 m2,m2c/m2 sideoverlap allMetal1 space nwell 60 allActive,allPoly sideoverlap allMetal1 space nwell 0 allActive,allPoly m2,m3c/m2 -28 sideoverlap allMetal1 space nwell 0 allActive,allPoly m3 -25 m2,m2c/m2 sideoverlap allMetal1 space pdiff,ndiff 60 sideoverlap allMetal1 space pdiff,ndiff 0 glass m2,m3c/m2 -28 sideoverlap allMetal1 space pdiff,ndiff 0 glass m3 -25 m2,m2c/m2 sideoverlap allMetal1 space nfet,pfet,poly 65 sideoverlap allMetal1 space nfet,pfet,poly 0 glass m2,m3c/m2 -29 sideoverlap allMetal1 space nfet,pfet,poly 0 glass m3 -22 m2,m2c/m2 sideoverlap allMetal1 space m2,m3c 31 glass sideoverlap allMetal1 space m2,m3c 0 glass nfet,pfet,poly -2 sideoverlap allMetal1 space m3 21 allMetal2 sideoverlap allMetal1 space m3 0 allMetal2 nfet,pfet,poly -1