* * Communications program for the Radio Shack Color Computer 1,2 * Receives up to 48K of data at 9600 baud * Times out after about 4 minutes with no incoming data, * and after a 10 second gap after recieving any * See "interesting results" for return values other than buffer * * 13-Sep-1986 101am WJY * 31-Jan-1996 1248nn WJY * 20-Feb-1998 8pm WJY - brought in synch with comm5s19 * BUFBEG equ $4000 buffer beginning address BUFEND equ $FF00 ending ACTIND equ $05FF activity indicator on screen S_IN_A equ $FF22 serial input address S_IN_B equ $01 serial input mask byte W1 equ $FF start-bit delays - gazillionths W2 equ $FA - jillionths W3 equ $F0 - seconds (roughly) * SAM addresses SAMVDG equ $FFC0 video display mode SAMDIS equ $FFC6 display address offset SAMPAG equ $FFD4 page #1 SAMRAT equ $FFD6 cpu rate SAMSIZ equ $FFDA memory size SAMTYP equ $FFDE memory map type org $3000 begin bra rstart fcb $98,$02,$21,$02,$00 revision data & time rstart sty y_tmp save .y and .u stu u_tmp orcc #$50 ignore interrupts sta SAMTYP+1 use 64K of RAM ldu #S_IN_A ldy #BUFBEG ldb #S_IN_B lda #W3 sta wait3 st2 bitb ,u test for start bit 4 \_ 7 beq strtbt 3 / lda #W2 sta wait2 st1 lda #W1 s_str1 bitb ,u test again 4 \_ 7 beq strtbt 3 / deca W1 loops 2 bne s_str1 3 bitb ,u test again 4 \_ 7 beq strtbt 3 / dec wait2 times W2 7 bne st1 3 bitb ,u test again 4 \_ 7 beq strtbt 3 / inc ACTIND activity indicator 7 bitb ,u test again 4 \_ 7 beq strtbt 3 / dec wait3 7 bne st2 times W3 3 lbra rdone no data, timed out, return * Need exactly 93 clock cycles between bits * 3 cycles were already used by the branch to get here, * and 7 more will be spent in the bit-check loop before checking strtbt ldd #$800D preset bit & delay count 3 \ sta byte 5 | s_str2 decb wait out start bit 2 \__ 65 | bne s_str2 3 / |- 83 inc ACTIND activity indicator 7 | brn s_bit waste three clock cycles 3 / s_bit ldx #0 check serial port for ones 3 ldb ,u check once 4 \ andb #S_IN_B 2 | abx 3 | * | ldb ,u check twice | andb #S_IN_B | abx | * | ldb ,u check thrice |- 72 andb #S_IN_B | abx | * | ldb ,u check 4 times | andb #S_IN_B | abx | * | ldb ,u check 5 times | andb #S_IN_B | abx | * | ldb ,u check 6 times | andb #S_IN_B | abx | * | ldb ,u check 7 times | andb #S_IN_B | abx | * | ldb ,u check 8 times | andb #S_IN_B | abx / nop 2 \ nop 2 | cmpx #5 did we get a one-bit? 4 |- 18 ror byte shift in negated bit 7 | bcc s_bit until the preset bit pops out 3 / * There must be at least one stop bit, so we have at least * 93 cycles to putter around here. (It is okay to finish sooner) lda byte 5 \ coma get the non-inverted bits 2 | sta ,y+ save 'em 6 | lda #10 2 |- 33 sta wait3 timeout is now 10 seconds 5 | ldb #S_IN_B restore .b, which got messed up 2 | cmpy #BUFEND 5 | lbne st2 if buffer isn't full, go get more 6 / rdone sty rlast note how much we got done ldy y_tmp restore registers .y and .u ldu u_tmp sta SAMTYP use ROMs again andcc #$AF re-enable interrupts rts org $3100 * interesting results rlast rmb 2 one past last buffer address received * internal temporary storage byte rmb 1 the byte being recieved y_tmp rmb 2 hold .y and .u while running u_tmp rmb 2 wait2 rmb 1 delay counters wait3 rmb 1 end begin