0001 * 0002 * Communications program for the Radio Shack Color Computer 1,2 0003 * Receives up to 48K of data at 9600 baud 0004 * Times out after about 4 minutes with no incoming data, 0005 * and after a 10 second gap after recieving any 0006 * See "interesting results" for return values other than buffer 0007 * 0008 * 13-Sep-1986 101am WJY 0009 * 31-Jan-1996 1248nn WJY 0010 * 20-Feb-1998 8pm WJY - brought in synch with comm5s19 0011 * 0012 0013 4000 BUFBEG equ $4000 buffer beginning address 0014 ff00 BUFEND equ $FF00 ending 0015 05ff ACTIND equ $05FF activity indicator on screen 0016 ff22 S_IN_A equ $FF22 serial input address 0017 0001 S_IN_B equ $01 serial input mask byte 0018 00ff W1 equ $FF start-bit delays - gazillionths 0019 00fa W2 equ $FA - jillionths 0020 00f0 W3 equ $F0 - seconds (roughly) 0021 0022 * SAM addresses 0023 ffc0 SAMVDG equ $FFC0 video display mode 0024 ffc6 SAMDIS equ $FFC6 display address offset 0025 ffd4 SAMPAG equ $FFD4 page #1 0026 ffd6 SAMRAT equ $FFD6 cpu rate 0027 ffda SAMSIZ equ $FFDA memory size 0028 ffde SAMTYP equ $FFDE memory map type 0029 0030 3000 org $3000 0031 0032 3000 20 05 begin bra rstart 0033 3002 98 02 21 02 00 fcb $98,$02,$21,$02,$00 revision data & time 0034 3007 10 bf 31 03 rstart sty y_tmp save .y and .u 0035 300b ff 31 05 stu u_tmp 0036 300e 1a 50 orcc #$50 ignore interrupts 0037 3010 b7 ff df sta SAMTYP+1 use 64K of RAM 0038 0039 3013 ce ff 22 ldu #S_IN_A 0040 3016 10 8e 40 00 ldy #BUFBEG 0041 0042 301a c6 01 ldb #S_IN_B 0043 301c 86 f0 lda #W3 0044 301e b7 31 08 sta wait3 0045 3021 e5 c4 st2 bitb ,u test for start bit 4 \_ 7 0046 3023 27 2a beq strtbt 3 / 0047 3025 86 fa lda #W2 0048 3027 b7 31 07 sta wait2 0049 302a 86 ff st1 lda #W1 0050 0051 302c e5 c4 s_str1 bitb ,u test again 4 \_ 7 0052 302e 27 1f beq strtbt 3 / 0053 3030 4a deca W1 loops 2 0054 3031 26 f9 bne s_str1 3 0055 3033 e5 c4 bitb ,u test again 4 \_ 7 0056 3035 27 18 beq strtbt 3 / 0057 3037 7a 31 07 dec wait2 times W2 7 0058 303a 26 ee bne st1 3 0059 303c e5 c4 bitb ,u test again 4 \_ 7 0060 303e 27 0f beq strtbt 3 / 0061 3040 7c 05 ff inc ACTIND activity indicator 7 0062 3043 e5 c4 bitb ,u test again 4 \_ 7 0063 3045 27 08 beq strtbt 3 / 0064 3047 7a 31 08 dec wait3 7 0065 304a 26 d5 bne st2 times W3 3 0066 304c 16 00 58 lbra rdone no data, timed out, return 0067 0068 * Need exactly 93 clock cycles between bits 0069 * 3 cycles were already used by the branch to get here, 0070 * and 7 more will be spent in the bit-check loop before checking 0071 304f cc 80 0d strtbt ldd #$800D preset bit & delay count 3 \ 0072 3052 b7 31 02 sta byte 5 | 0073 3055 5a s_str2 decb wait out start bit 2 \__ 65 | 0074 3056 26 fd bne s_str2 3 / |- 83 0075 3058 7c 05 ff inc ACTIND activity indicator 7 | 0076 305b 21 00 brn s_bit waste three clock cycles 3 / 0077 0078 305d 8e 00 00 s_bit ldx #0 check serial port for ones 3 0079 0080 3060 e6 c4 ldb ,u check once 4 \ 0081 3062 c4 01 andb #S_IN_B 2 | 0082 3064 3a abx 3 | 0083 * | 0084 3065 e6 c4 ldb ,u check twice | 0085 3067 c4 01 andb #S_IN_B | 0086 3069 3a abx | 0087 * | 0088 306a e6 c4 ldb ,u check thrice |- 72 0089 306c c4 01 andb #S_IN_B | 0090 306e 3a abx | 0091 * | 0092 306f e6 c4 ldb ,u check 4 times | 0093 3071 c4 01 andb #S_IN_B | 0094 3073 3a abx | 0095 * | 0096 3074 e6 c4 ldb ,u check 5 times | 0097 3076 c4 01 andb #S_IN_B | 0098 3078 3a abx | 0099 * | 0100 3079 e6 c4 ldb ,u check 6 times | 0101 307b c4 01 andb #S_IN_B | 0102 307d 3a abx | 0103 * | 0104 307e e6 c4 ldb ,u check 7 times | 0105 3080 c4 01 andb #S_IN_B | 0106 3082 3a abx | 0107 * | 0108 3083 e6 c4 ldb ,u check 8 times | 0109 3085 c4 01 andb #S_IN_B | 0110 3087 3a abx / 0111 0112 3088 12 nop 2 \ 0113 3089 12 nop 2 | 0114 308a 8c 00 05 cmpx #5 did we get a one-bit? 4 |- 18 0115 308d 76 31 02 ror byte shift in negated bit 7 | 0116 3090 24 cb bcc s_bit until the preset bit pops out 3 / 0117 0118 * There must be at least one stop bit, so we have at least 0119 * 93 cycles to putter around here. (It is okay to finish sooner) 0120 3092 b6 31 02 lda byte 5 \ 0121 3095 43 coma get the non-inverted bits 2 | 0122 3096 a7 a0 sta ,y+ save 'em 6 | 0123 3098 86 0a lda #10 2 |- 33 0124 309a b7 31 08 sta wait3 timeout is now 10 seconds 5 | 0125 309d c6 01 ldb #S_IN_B restore .b, which got messed up 2 | 0126 309f 10 8c ff 00 cmpy #BUFEND 5 | 0127 30a3 10 26 ff 7a lbne st2 if buffer isn't full, go get more 6 / 0128 0129 30a7 10 bf 31 00 rdone sty rlast note how much we got 0130 30ab 10 be 31 03 done ldy y_tmp restore registers .y and .u 0131 30af fe 31 05 ldu u_tmp 0132 30b2 b7 ff de sta SAMTYP use ROMs again 0133 30b5 1c af andcc #$AF re-enable interrupts 0134 30b7 39 rts 0135 0136 3100 org $3100 0137 0138 * interesting results 0139 3100 rlast rmb 2 one past last buffer address received 0140 0141 * internal temporary storage 0142 3102 byte rmb 1 the byte being recieved 0143 3103 y_tmp rmb 2 hold .y and .u while running 0144 3105 u_tmp rmb 2 0145 3107 wait2 rmb 1 delay counters 0146 3108 wait3 rmb 1 0147 0148 end begin Number of errors 0