AS09 Assembler for M6809/H6309 [1.11]. Page 1 --------------------------------- COMM6.ASM ---------------------------------- 330 lines read, no errors in pass 1. * * Communications program for the Radio Shack Color Com * Receives up to 48K of data at 38400 baud * Times out after 4 minutes with no incoming data, * and after a 10 second gap after recieving any * See "interesting results" for return values other th * * 13-Sep-1986 101am WJY * 31-Jan-1996 1248nn WJY * 21-Feb-1998 2am WJY - brought in synch with comm5s19 * 25-Sep-1999 345am WJY - from COMM4 * 29-Sep-1999 3am WJY - fixed sample timing * 29-Sep-1999 330am WJY - at end, rlast = .x, not .y * - also fixed time-out delays * noopt include "coco.asm" nolist 4000 = BUFBEG equ $4000 ; buffer beginning address ff00 = BUFEND equ $FF00 ; ending ff22 = S_IN_A equ PIA1BD ; serial input address 0001 = S_IN_B equ $01 ; serial input mask byte 00ff = W1 equ 255 ; start-bit delays - gazillionths 00b7 = W2 equ 183 ; - jillionths 00f0 = W3 equ 240 ; - seconds 3000 = org $3000 3000 : 200f begin bra rstart 3002 : 9909290330 fcb $99,$09,$29,$03,$30 ; revision date & time 3007 : 434f4d4d362056.. fcc "COMM6 V0.3" 3011 : 10bf3103 rstart sty y_tmp ; save .y and .u 3015 : ff3105 stu u_tmp 3018 : 1a50 orcc #(IRQ|FIRQ) ; ignore interrupts 301a : b7ffdf sta SAMTYP+1 ; use 64K of RAM 301d : 8e4000 ldx #BUFBEG 3020 : ceff22 ldu #S_IN_A ; constant 3023 : c601 ldb #S_IN_B 3025 : 86f0 lda #W3 3027 : b73108 sta wait3 * Watch for the start bit. * Sample the incoming bit at least once every 12 cycle * Whatever other work we do here, such as counting dow * a time-out, must be interleaved with start-bit sampl * initialize counters 302a : e5c4 st2 bitb ,u ; test for start bit 302c : 2764 beq strtbt ; 3 302e : 86b7 lda #W2 ; 2 / 3030 : e5c4 bitb ,u ; test again 4 \ 3032 : 275e beq strtbt ; 3 3034 : b73107 sta wait2 ; 5 3037 : e5c4 st1 bitb ,u ; test again 4 3039 : 2757 beq strtbt ; 3 AS09 Assembler for M6809/H6309 [1.11]. Page 2 --------------------------------- COMM6.ASM ---------------------------------- 303b : 86ff lda #W1 ; 2 / * count down in .a 303d : e5c4 s_str1 bitb ,u ; test again 303f : 2751 beq strtbt ; 3 3041 : e5c4 bitb ,u ; test again 4 \ 3043 : 274d beq strtbt ; 3 3045 : 4a deca ; W1 loops 2 | 3046 : 26f5 bne s_str1 ; 3 * count down in wait2 3048 : e5c4 bitb ,u ; test again 4 \ 304a : 2746 beq strtbt ; 3 304c : b63107 lda wait2 ; 5 304f : e5c4 bitb ,u ; test again 4 \ 3051 : 273f beq strtbt ; 3 3053 : 4a deca ; times W2 2 / 3054 : e5c4 bitb ,u ; test again 4 \ 3056 : 273a beq strtbt ; 3 3058 : b73107 sta wait2 ; 5 305b : e5c4 bitb ,u ; test again 4 \ 305d : 2733 beq strtbt ; 3 305f : 4d tsta ; 2 | 3060 : 26d5 bne st1 ; 3 / * increment the activity indicator 3062 : e5c4 bitb ,u ; test again 4 \ 3064 : 272c beq strtbt ; 3 3066 : b605ff lda ACTIND ; activity indicator 5 3069 : e5c4 bitb ,u ; test again 4 \ 306b : 2725 beq strtbt ; 3 306d : 4c inca ; 2 / 306e : e5c4 bitb ,u ; test again 4 \ 3070 : 2720 beq strtbt ; 3 3072 : b705ff sta ACTIND ; 5 * count down in wait3 3075 : e5c4 bitb ,u ; test again 4 \ 3077 : 2719 beq strtbt ; 3 3079 : b63108 lda wait3 ; 5 307c : e5c4 bitb ,u ; test again 4 \ 307e : 2712 beq strtbt ; 3 3080 : 4a deca ; 2 / 3081 : e5c4 bitb ,u ; test again 4 \ 3083 : 270d beq strtbt ; 3 3085 : b73108 sta wait3 ; 5 3088 : e5c4 bitb ,u ; test again 4 \ 308a : 2706 beq strtbt ; 3 308c : 4d tsta ; 2 | 308d : 269b bne st2 ; times W3 3 / * all three counters went to zero; time-out 308f : 160038 lbra rdone ; no data, timed out, return * 894886.2 clock cycles per second / 38400 bits per se * Need exactly 23.3043281 clock cycles between bits. * Call it 23.3, and try to minimize error in successiv * The sample that noticed the start bit could be anywh * from 1 to 12 cycles into that. In addition to the t * we pass to let the rest of the start bit go by, pass AS09 Assembler for M6809/H6309 [1.11]. Page 3 --------------------------------- COMM6.ASM ---------------------------------- * half of the slack time so the eight data bits will b * sampled near their centers. * But each bit sample is taken 7 clock cycles late, af * a 'bsr'. So compensate by starting the sampling 7 c * earlier. * Ie: 23.3 - 12 = 11.3 slack, half of that is 5.65. * 7 cycles have already passed since the start of the * start-bit sample (bitb & beq), so there are 16.3 cyc * left in the start bit. * delay 16.3 + 5.65 - 7 = 14.95 cycles. 3092 : bc3100 strtbt cmpx rlast ; 3095 : 10bc3100 cmpy rlast ; 8 * bit 1: 3099 : 8d3f bsr getbit ; get a bit 21 309b : 12 nop ; pass some time 2 / * wanted to pass 23.3 cycles, actually passed only 23 * we are now .3 cycles early * bit 2: 309c : 8d3c bsr getbit ; get a bit 21 309e : 213a brn getbit ; pass some time 3 * wanted to pass 23.6 cycles, actually passed 24 * we are now .4 cycles late * bit 3: 30a0 : 8d38 bsr getbit ; get a bit 21 30a2 : 12 nop ; pass some time 2 / * wanted to pass 22.9 cycles, actually passed 23 * we are now .1 cycles late * bit 4: 30a3 : 8d35 bsr getbit ; get a bit 21 30a5 : 12 nop ; pass some time 2 / * wanted to pass 23.2 cycles, actually passed only 23 * we are now .2 cycles early * bit 5: 30a6 : 8d32 bsr getbit ; get a bit 21 30a8 : 12 nop ; pass some time 2 / * wanted to pass 23.5 cycles, actually passed only 23 * we are now .5 cycles early * bit 6: 30a9 : 8d2f bsr getbit ; get a bit 21 30ab : 212d brn getbit ; pass some time 3 * wanted to pass 23.8 cycles, actually passed 24 * we are now .2 cycles late * bit 7: 30ad : 8d2b bsr getbit ; get a bit 21 30af : 12 nop ; pass some time 2 / * wanted to pass 23.1 cycles, actually passed only 23 * we are now .1 cycles early AS09 Assembler for M6809/H6309 [1.11]. Page 4 --------------------------------- COMM6.ASM ---------------------------------- * bit 8: 30b0 : bc3100 cmpx rlast ; pass as much time as bsr 7 30b3 : f6ff22 ldb S_IN_A ; sample incoming bit 5 30b6 : 56 rorb ; move incoming bit to .cc.c 2 | 30b7 : 46 rora ; shift bit into byte 2 / * wanted to pass 23.4 cycles, actually passed only 16 * we are now 7.4 cycles early * Plus, all 8 sample 'bsr's were 7 cycles early, so we * have 7 extra cycles to fool around here, making a gr * total of 14.4 cycles early. * We have at least one stop bit, or 23.3 cycles * since we arrived so early, we actually have at * least 37.7 cycles. Being earlier is better here; * It is no problem if we get back to watching for * a start bit before this stop bit is completed. 30b8 : a780 sta ,x+ ; save 'em 6 \ 30ba : b705ff sta ACTIND ; show the data as it arrives 5 30bd : cc0a01 ldd #(10<<8)|S_IN_B ; 3 30c0 : b73108 sta wait3 ; timeout is now 10 seconds 5 30c3 : 8cff00 cmpx #BUFEND ; 4 30c6 : 1026ff60 lbne st2 ; if buffer isn't full, go get more 6 / 30ca : bf3100 rdone stx rlast ; note how much we got 30cd : 10be3103 done ldy y_tmp ; restore registers .y and .u 30d1 : fe3105 ldu u_tmp 30d4 : b7ffde sta SAMTYP ; use ROMs again 30d7 : 1caf andcc #~(IRQ|FIRQ) ; re-enable interrupts 30d9 : 39 rts * bsr getbit ; 7 30da : f6ff22 getbit ldb S_IN_A ; sample incoming bit 30dd : 56 rorb ; move incoming bit to .cc.c 2 |- 30de : 46 rora ; shift bit into byte 2 | 30df : 39 rts ; 5 / 3100 = org $3100 * interesting results 3100 : 0000 rlast rmb 2 ; one past last buffer address received * internal temporary storage 3102 : 00 byte rmb 1 ; the byte being recieved 3103 : 0000 y_tmp rmb 2 ; hold .y and .u while running 3105 : 0000 u_tmp rmb 2 3107 : 00 wait2 rmb 1 ; delay counters 3108 : 00 wait3 rmb 1 3108 = end begin No errors in pass 2.