MP-B2 board
The MP-B2 is the mother board in a 6800 system.
It has a set of fifty parallel traces to carry the signals of the SS-50
bus, and another set of thirty for the SS-30 I/O bus.
Because these machines were often sold in the form of kits, the traces
are each labelled, allowing one to see which signal is on which line.
There are only a few IC's on the board, but mostly just the male Molex
connectors onto which the computer boards plug in.
Here is a list of the IC's:
- 7805 (5v voltage regulator)
- NS 8835 [x2] (don't remember, will have to hit the databooks)
- 7400 (quad 2-in NAND)
- 7402 (quad 2-in NOR)
- 74S138 [x2] (three-to-eight line decoder)
- 74367 (hex tri-state buffer)
Below are lists of the names attached to each line.
MP-B2 SS-50 Signals
- *D0 - (complement) data bus line 0
- *D1 "
- *D2 "
- *D3 "
- *D4 "
- *D5 "
- *D6 "
- *D7 - (complement) data bus line 7
- A15 - address bus line 15
- A14 "
- A13 "
- A12 "
- A11 "
- A10 "
- A9 "
- A8 "
- A7 "
- A6 "
- A5 "
- A4 "
- A3 "
- A2 "
- A1 "
- A0 - address bus line 0
- GND - ground
- GND - ground
- GND - ground
- 7-8 VDC UNREG - power line
- 7-8 VDC UNREG - power line
- 7-8 VDC UNREG - power line
- -12V - power line
- +12V - power line
- INDEX - no pin - prevents backwards insertion
- *M.RST - manual reset
- *NMI - (complement) non-maskable interrupt
- *IRQ - (complement) interrupt request
- UD2 - user-defined
- UD1 - user-defined
- *Phase 2 (complement) clock
- *VMA - (complement) Valid Memory Address
- R/*W - Read / (complement) Write
- *Reset - (complement) Reset or power-up
- BA - Bus Available for DMA
- Phase 1 clock
- *Halt - (complement) halts the processor
- 110b
- 150b
- 300b
- 600b
- 1200b
MP-B2 SS-30 Signals
- UD3 - user-defined
- UD4 - user-defined
- -12 - power line
- +12 - power line
- GND - ground
- GND - ground
- INDEX - no pin - prevents backwards insertion
- *NMI - (complement) non-maskable interrupt
- *IRQ - (complement) interrupt request
- RS0 - register select 0 - like A0
- RS1 - register select 1 - like A1
- D0 - data bus line 0
- D1 "
- D2 "
- D3 "
- D4 "
- D5 "
- D6 "
- D7 - data bus line 7
- Phase 2 - (not complemented?) clock
- R/*W - Read / (complement) Write
- +8 UNR - power line
- +8 UNR - power line
- 1200b - 1200 baud clock signal
- 4800b - 4800 "
- 300b - 300 "
- 9600b - 9600 "
- 110b - 110 baud clock signal
- *RESET - (complement) Reset or power-up
- Board Select
21-Feb-1999
yakowenk@csx.unxc.edu
(remove all "x"s to get a valid address)