Hardware Security @ UNC
I lead the Hardware Security @ UNC lab, where we develop tools for the formal analysis of hardware designs. Our research aims to identify critical security vulnerabilities before designs are fabricated. You can find our most recent papers in the research section.Check out our recent work on GitHub:
- Repository of security properties for the formal verification of open-source processors and SoCs.
- Sylvia, the symbolic execution engine for Verilog designs; introduces piecewise composition to mitigate path explosion.
- SylQ-SV, the latest symbolic execution engine for SystemVerilog designs; uses query caching to improve performance.
Join the lab!
If you are a current UNC CS undergraduate, MS, or PhD student interested in the type of work we do, email or come by my office hours.