Hardware Security @ UNC
I lead the Hardware Security @ UNC lab. We build tools for the formal analysis of hardware designs. The goal of our research is to find the security flaws in hardware before the design is fabricated. Find our most recent papers under research above.Check out our recent work on GitHub:
- Repository of security properties for the formal verification of open-source processors and SoCs
- Sylvia, the symbolic execution engine for Verilog designs
- SylQ-SV, the latest symbolic execution engine for SystemVerilog designs, using query caching for improved performance.
Join the lab!
If you are a current UNC CS undergraduate, MS, or PhD student interested in the type of work we do, email or come by my office hours.