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Hardware Security @ UNC

I lead the Hardware Security @ UNC lab. We build tools for the formal analysis of hardware designs. The goal of our research is to find the security flaws in hardware before the design is fabricated.

Check out our repository of security properties for the formal verification of open-source processors and SoCs, and Sylvia, our symbolic execution engine for Verilog designs.

Join the lab!

If you are a current UNC CS undergraduate, MS, or PhD student interested in the type of work we do, email or come by my office hours.

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