M. Singh and S.M. Nowick.  “The Design of High-Performance Dynamic Asynchronous Pipelines:  Lookahead Style.”  To appear in IEEE Transactions on VLSI Systems (TVLSI), 14 pages, accepted November 2006.

M. Singh and S.M. Nowick.  “The Design of High-Performance Dynamic Asynchronous Pipelines:  High-Capacity Style.”  To appear in IEEE Transactions on VLSI Systems (TVLSI), 14 pages, accepted November 2006.

M. Singh and S.M. Nowick.  “MOUSETRAP:  High-Speed Transition-Signaling Asynchronous Pipelines.”  To appear in IEEE Transactions on VLSI Systems (TVLSI), 14 pages, accepted October 2006.  

M. Singh and S.M. Nowick.  "Synthesis for Logical Initializability of Synchronous Finite State Machines."  IEEE Transactions on VLSI Systems (TVLSI), vol. 8, no. 5, pages 542-557, October 2000.  

M. Singh, A. Chatterjee, and S. Chaudhury.  “Matching Structural Shape Descriptions Using Genetic Algorithms.”  Pattern Recognition, vol. 30, no. 9, pages 1451-1462, September 1997 (Elsevier Science, UK).

G.Gill, J. Hansen and M. Singh.  “Loop Pipelining for High-Throughput Stream Computation Using Self-Timed Rings.”  Proc. of Intl. Conf. on Computer-Aided Design (ICCAD-06), San Jose , CA , November 2006.  

M. Ampalam and M. Singh.  “Counterflow Pipelining:  Architectural Support for Preemption in Asynchronous Systems using Anti-Tokens.”  Proc. of Intl. Conf. on Computer-Aided Design (ICCAD-06), San Jose , CA, November 2006.  

G. Gill, A. Agiwal, M. Singh, F. Shi, and Y. Makris.  “Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines.”  Proc. of the 12^th IEEE Intl. Symp. on Async. Circ. and Syst. (ASYNC-06), Grenoble , France , March 2006.  

A. Agiwal and M. Singh.  “An Architecture and Wrapper Synthesis for Multi-Clock Latency-Insensitive Systems.”  Proc. of Intl. Conf. on Computer-Aided Design (ICCAD-05), San Jose, CA , November 2005.

F. Shi, Y. Makris, S.M. Nowick and M. Singh.  “Test Generation for Ultra-High-Speed Asynchronous Pipelines.”  Proc. of Intl. Test Conference (ITC-05), Austin , TX , November 2005.  

J. Hensley, T. Scheuermann, G. Coombe, A. Lastra and M. Singh.  “Fast Summed-Area Table Generation and its Applications.”  Proc. of Eurographics 2005, Dublin , Ireland , August 2005.  

J. Hensley, M. Singh, A. Lastra.  “A Fast, Energy-Efficient Z-Comparator.”  Proc. of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware (GHW-05), Los Angeles , CA , July 2005.  

A. Agiwal and M. Singh.  “Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis.”  Proc. of the Second Intl. Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design (FMGALS-05), in cooperation with ACM SIGDA and SIGARCH, Verona, Italy, July 2005.  Published in Electronic Notes in Theoretical Computer Science, vol. 146, no. 2, January 2006.  (ISSN: 1571-0661, Elsevier)  

J. Hensley, A. Lastra and M. Singh.  “A Scalable Counterflow-Pipelined Asynchronous Radix-Four Booth Multiplier.”  Proc. of the 11^th IEEE Intl. Symp. on Async. Circ. and Syst. (ASYNC-05), New York City , NY, March 2005.   

J. Hensley, A. Lastra and M. Singh.  “An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices.”  Proc. of IEEE Intl. Conf. on Computer Design (ICCD-04), San Jose , CA , October 2004.  

M. Singh and M. Theobald.  “Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures.”  Proc. of ACM/IEEE Design, Automation and Test in Europe (DATE-04), Paris , France, February 2004.

M. Singh, J.A. Tierno, A. Rylyakov, S. Rylov, and S.M. Nowick.  "An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz."  Proc. of the 8^th IEEE Intl. Symp. on Async. Circ. and Syst. (ASYNC-02), Manchester , UK , April 2002.  (Best Paper Finalist)  

R.O. Ozdag, M. Singh, P.A. Beerel, and S.M. Nowick.  "High-Speed Non-Linear Asynchronous Pipelines."  Proc. of Design, Automation and Test in Europe (DATE-02), Paris , France , March 2002.  

J. Tierno, A. Rylyakov, S. Rylov, M. Singh, P. Ampadu, S.M. Nowick, M. Immediato, and S. Gowda.  "A 1.3 GSample/s 10-tap Full-rate Variable-latency Self-timed FIR filter with Clocked Interfaces."  Proc. of IEEE Intl. Solid-State Circ. Conf. (ISSCC-02), San Francisco, CA, February 2002.  

M. Singh and S.M. Nowick.  "MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines."  Proc. of IEEE Intl. Conf. on Computer Design (ICCD-01), Austin , TX , September 2001.  

M. Singh and S.M. Nowick.  "High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths."  Proc. of the 6^th IEEE Intl. Symp. on Adv. Res. in Async. Circ. and Syst. (ASYNC-2000), Eilat , Israel , April 2000.  (Received Best Paper Award)  

M. Singh and S.M. Nowick.  "Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications."  Proc. of IEEE Computer Society Annual Workshop on VLSI (WVLSI-2000), pp. 111-118, Orlando , FL , April 2000.  (IEEE Computer Society Press, ISBN: 0-7695-0534-1)  

M. Singh and S.M. Nowick.  “Synthesis for Logical Initializability of Synchronous Finite State Machines.”  Proc. of the Tenth Intl. Conf. on VLSI Design (VLSID-97), Hyderabad , India , January 1997.  

M. Singh and S.M. Nowick.  "Synthesis for Initializability of Asynchronous Sequential Machines."  Proc. of the Intl. Test Conference (ITC-96), Washington, DC, October 1996. 

G. Gill and M. Singh.  “Robust Synthesis of Asynchronous Burst-Mode Machines.”  Proc. of the 14^th Intl. Workshop on Logic and Synthesis (IWLS-05), Lake Arrowhead , CA , June 2005.  

G. Gill and M. Singh.  “Synthesizing Asynchronous Burst-Mode Machines without the Fundamental-Mode Timing Assumption.”  Proc. of the ACM/IEEE Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-05), San Francisco, CA, February 2005.  

M. Singh and M. Theobald.  “Generalized Latency-Insensitive Systems for GALS Architectures.”  Proc. of the Workshop on Formal Methods for Globally Asynchronous Locally Synchronous (GALS) Architecture (FMGALS-03), held in conjunction with the 12th International Formal Methods Europe Symposium, Pisa , Italy , September 2003.  

M. Singh and S.M. Nowick.  “MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines.”  Proc. of the ACM/IEEE Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-2000), Austin, TX, December 2000.  

Stephen B. Furber, A. Efthymiou and M. Singh.  "A Power-Efficient Duplex Communication System."  Workshop on Asynchronous Interfaces:  Tools, Techniques and Implementations, TU Delft, the Netherlands , July 2000.  

Montek Singh and Steven M. Nowick.  “State Assignment for Initializability of Synchronous Finite State Machines.”  IEEE Intl. Test Synthesis Workshop (ITSW-06), Santa Barbara , CA , May 1996.

J. Hensley, T. Scheuermann, M. Singh, and A. Lastra.  “Fast Summed-Area Table Generation for Glossy Environmental Reflections,” Sketch presented at SIGGRAPH 2005, Los Angeles , CA , August 2005.  

J. Hensley, T. Scheuermann, M. Singh, and A. Lastra.  “Fast, Approximate HDR Image-Based Lighting Using Summed-Area Tables.”  Poster to be presented at Symposium on Interactive 3D Graphics and Games (i3D-07), Seattle, WA, April 2007.  

G. Gill and M. Singh.  “Ray Tracing on Asynchrounous Supercomputing Stream Processors.”  Poster presented at the IEEE Symposium on Interactive Ray Tracing, Salt Lake City , Utah , September 2006.  

G. Gill, J. Hansen and M. Singh.  “High-Throughput Looping in Stream Processors Using Self-Timed Architectures.”  Poster and abstract at the Workshop on Edge Computing Using New Commodity Architectures (EDGE), Chapel Hill , NC , May 2006.  

M. Singh, “The Design of High-Speed Asynchronous Pipelines.”  Poster presented at the ACM SIGDA Ph.D. Forum, held in conjunction with the Design Automation Conference (DAC-01), Las Vegas, NV, June 2001.