Predicting Worst Case Execution Times on a Pipelined RISC Processor

S. Bharrat and K. Jeffay
Technical Report TR94-072,
Department of Computer Science,
University of North Carolina at Chapel Hill,
April 1994.

Abstract: A key step in analyzing and reasoning about the performance of real-time systems is the derivation of the worst case execution time of a program or program fragment. Modern computer systems with pipelined processors, caches, DMA, etc., can complicate this process. We demonstrate that pipelining need not be considered to be a barrier to the computation of useful worst case execution time bounds of programs by developing a simple method for accounting for the speed-up due to pipelining in an implementation of the Sparc RISC processor architecture. The method is applied to several non-trivial program fragments and is capable of accurately measuring worst case execution time even when programs are delayed by interrupt processing.

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