VLSI Course Release Notes

This page contains some retrospective thoughts on the attached VLSI course notes written almost exactly two years after the completion of the course itself. By and large, we are still happy with the presentation of the material in the notes. We describe here a few things that might be done differently next time.

There are references sprinkled through the slides to various "Chapters". These refer to the textbook used with the course, "CMOS Circuit Design, Layout, and Simulation," by Baker, Li, and Boyce, published by IEEE Press. This book turned out not to be a great choice for our course, though it has lots of interesting material in it, particularly on the subject of analog CMOS. In retrospect, we wish we'd used Jan Rabaey's book "Digital Integrated Circuits, A Design Perspective", published by Prentice Hall. This book is one of the better introductory texts in VLSI design available today.

The sections on the tau model (mainly Lecture 9) could have been done better. By way of excuse, nearly all of the authors of VLSI introductory textbooks get this at least partially wrong. We hope to do better, if we ever have the opportunity to teach this material again.

The example technology we used throughout the course is Hewlett- Packard's CMOS14, a 0.5-micron, 3-metal CMOS technology that was the workhorse of academic VLSI in the 90's. This technology is now quite dated, of course. Most current designs are done in 0.25-micron, or more likely 0.18-micron rules, and fabricated on processes with 6 levels of metal. Power supplies have dropped from the 3.3 volts of CMOS14 to 1.8 volts.

Some of the most striking changes in the evolution of CMOS fabrication technologies are these:

  1. Wiring parasitics now make up a much larger percentage of the load that a typical CMOS stage must drive than in earlier 0.5-micron designs. Accurate interelectrode capacitance extraction is now much more important than it was for earlier technologies. Our work at UNC on MAGIC's extractor in the mid-90's greatly improved its ability to handle such structures, but we will soon have to revisit this problem, if we are to continue to use this excellent tool. While MAGIC's circuit extractor can still do a good job of estimating wiring capacitances, serious designs should supplement MAGIC with a commercial extractor to better estimate the parasitics in critical circuits.
  2. Device speed has not increased with shrinking device geometries as fast as in previous generations of CMOS fabrication. In fact, some 0.18-micron processes are about the same speed, or even slower, than their 0.25-micron predecessors. While this is mainly due to lower power supply voltages, it may also be a result of market forces; most ASIC customers appear to want higher density, not higher speed.
  3. I/O speeds (I/O circuits are covered in Lecture 24) are now limited primarily by the ESD primary devices. Diodes are no longer used as primary devices, because the very shallow junctions of modern CMOS processes don't provide a sufficiently robust diode. Instead, FETs, drawn slightly longer than minimum size, are used, and their non-linear (breakdown) characteristics are exploited to provide protection. The drains of these devices must be drawn very large, thus placing ever larger capacitance on I/O connections.

Steve Tell and John Pouton,
May, 2000