# Problem Set 2

| categories: Problem Sets

Due Wednesday 28 September at the beginning of class.

## Problem 1: Converting from Assembly Language to Instructions (45 points)

The conversion of a mnemonic instruction to its binary representation is called assembly. This tedious process is generally delegated to a computer program for a variety of reasons. In the following exercises, you will get a taste of what the task of translating from assembly to machine language is like.

Match the instructions below with their hexadecimal counterparts. Record your answers as the letter ‘A’-‘O’ that corresponds to the numbered instruction.

AssemblyHex Instruction
1: addi \$v0,\$zero,0x8009 A: 0x000A4A40
2: slti \$t2,\$t1,-1 B: 0x21490009
3: addi \$t1,\$t2,9 C: 0x014B4820
4: loop: bne \$t1,\$t2,loop D: 0x014B4824
5: loop2: beq \$t2,\$t1,loop2 E: 0x000A4A43
6: sll \$t1,\$t2,9 F: 0x3C094809
7: and \$9,\$10,\$11 G: 0x152AFFFF
8: ori \$t1,\$t2,9 H: 0x292AFFFF
9: lw \$a1,0x09(\$v0) I: 0x312A4809
10: add \$t1,\$t2,\$t3 J: 0x3C03FFFF
11: andi \$t2,\$t1,0x4809 K: 0x20028009
12: lui \$t1,0x4809 L: 0x020A4820
13: lui \$v1,0xFFFF M: 0x8C450009
14: sra \$t1,\$t2,9 N: 0x1149FFFF
15: add \$t1,\$s0,\$t2 O: 0x35490009

## Problem 2: Converting pseudo-instructions (35 points)

MIPS assembly language provides opcode mnemonics for instructions that are not part of the instruction set architecture. For the most part, these pseudoinstructions can be generated using a sequence of one or more “true” MIPS instructions.

Find a “true-instruction” equivalent for each of the following pseudo-instructions (some are official MIPS pseudoinstructions, others are made up). Each of these can be implemented using only one real MIPS instruction. Discuss of your implementations, if any, and whether or not your implementation is unique (i.e. could some other instruction be used to achieve the same effect).

1. move rA, rB
Reg[rA] ← Reg[rB]
Move register rB to rA
2. not rA, rB
Reg[rA] ← ~Reg[rB]
Put the bitwise complement of rB into rA
3. neg rA, rB
Reg[rA] ← -Reg[rB]
Put the 2’s complement of rB into rA
4. dec rA
Reg[rA] ← Reg[rA] - 1
Decrement rA by 1 and place result in rA
5. Suppose we wanted to fill a register rA with the value 65535 (0x0000FFFF). Would the instruction addi rA,\$0,0xFFFF perform that action? If not, what would be the value in rA?
6. Suppose we wanted to fill a register rA with the value 255 (0x000000FF). Would the instruction ori rA,\$0,255 perform that operation? If not, what would be the value in rA?
7. Suppose we wanted to fill a register rA with the value -1 (0xFFFFFFFF). Would the instruction ori rA,\$0,-1 perform that operation? If not, what would be the value in rA?

## Problem 3. Loading up at the Store (20 points)

The MIPS ISA provides access to memory exclusively through load (lw) and store (sw) instructions. Both instructions are encoded using the I-format, thus providing three operands, two registers and a 16-bit sign-extended constant. The memory address is computed by adding the contents of the register specified in the rs register field to the sign-extended 16-bit constant. Then either the contents of the specified memory location are loaded in the register specified in rt instruction field (lw), or that register’s contents are stored in the indicated memory location (sw).

It is possible to “directly” address a limited range of 32-bit memory locations by encoding the rs field as \$0.

1. How many distinct memory locations can be addressed this way? (Note: Addresses generated by lw/sw instructions must be multiples of 4, i.e., they must be word addresses.)
2. MIPS assemblers provide a pseudoinstruction (see problem 2) called “la” for load address for loading an effective address into a register . The syntax of this pseudoinstruction matches the lw instruction. Here is an example: la \$t0, 100(\$t1). What actual instruction can be used to implement this pseudoinstruction?