Our last exam will be Wednesday 30 November. It will cover everything up to and including the first part of lecture 17 with emphasis on lectures 11 through 17.
- You know you'll get some questions about stuff in the problem sets. Though never at the painful level of detail in those.
- I'll likely include a question from Problem Set 6 but it won't involve tracing wires on the diagram. More like, "What does this signal do?"
- Memory questions will be high level, never about circuit diagrams. But you should be ready to talk about the differences between (say) DRAM and SRAM.
- Finite State Machines are great fodder for questions, particularly when representing the state transition table as a ROM.
- Pipelining questions will be about how much you can expect to gain, and identifying the hazards.
- We won't deal with Cache and VM questions until the quiz at the end of class on the final day.