Palmer, R., Poulton, J., Leibowitz, B., Frans, Y, Li, S., Fuller, A., Eyles, J. Wilson, J., Aleksic, M, Greer, T., Bucher, M., Nguyen, N., "A 4.3GB/s Mobile Memory Interface with Power-efficient Bandwidth Scaling," Proceedings of 2009 Symposium on VLSI Circuits, June 16-18, 2009, pp 136-137.

Poulton, J., Palmer, R., Fuller, A., Greer, T., Eyles, J., Dally, W. and Horowitz, M.., "A 14mW 6.25Gb/s Transceiver in 90-nm CMOS," Proceedings of the IEEE Journal of Solid State Circuits, Dec. 2007, pp 2745-2757. Winner, Best Paper Award for 2007.

Palmer, R., Poulton, J., Dally, W., Eyles, J., Fuller, A., Greer, T., Horowitz, M. Kellam, M., Quan, F., Zarkeshvari, F., "A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications," Proceedings of the International Solid State Circuits Conference, Feb. 2007, pp 440-441.

Ng, H-T, Lee, M.-J., Farjad-Rad, R., Senthinathan, R., Dally, W., Nguyen, A., Rathi, R., Greer, T., Poulton, J., Edmondson, J., and Tran, J., "A 33mW 622 Mb/s-8Gb/s CMOS CDR for Highly Integrated I/Os," to appear in 2003 IEEE Symposium on VLSI Circuits, June 2003.

Lee, M.-J., Dally, W., Greer, T., Ng, H.-T., Farjad, R., Poulton, J., and Senthinathan, R., "Jitter Transfer Characteristics of Delay-Locked Loops-Theories and Design Techniques Proceedings of IEEE Journal of Solid State Circuits, Vol 38, No. 4, pp 614-621, April 2003.

Farjad-Rad, R., Dally, W., Ng, H-T, Senthinathan, R., Lee, M.-J., Rathi, R., and Poulton, J, "A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly Integrated Digital Chip," Proceedings of IEEE Journal of Solid State Circuits, Vol 37, No. 12, pp.1804-1812, December 2002.

Farjad-Rad, R., Dally, W., Ng, H-T, Poulton, J., Stone, T., Rathi, R., Lee, E., Huang, D. and Nathan, R., "A 0.2-2GHz 12mW Multiplying DLL for Low-Jitter Clock Synthesis in High-Integrated Data Communications Chips," Proceedings of 2002 International Solid State Circuits Conference, pp 76-77.

Lee, M.-J., Dally, W., Poulton, J., Chiang, P., and Greenwood, S., "An 84-mW 4-Gb/s Clock and Data Recovery Circuit for Serial Link Applications," Proceedings of the IEEE Symposium on VLSI Circuits, June 2001.

Poulton, J., "Problems and Prospects for Electrical Signaling," invited presentation, Proceedings of the 1999 Conference on Advanced Research in VLSI, Atlanta Georgia, March 21-24, 1999.

Poulton, J., "Signaling in High Performance Memory Systems," Tutorial presented at ISSCC, San Francisco, CA, February, 1999.

Dally, William J., and Poulton, John W., "Digital Systems Engineering," Cambridge University Press, 1998.

Poulton, J., "An Embedded DRAM for CMOS ASICs," Proceedings of the 17th Conference on Advanced Research in VLSI, IEEE Computer Society Press, Sept 15-16, 1997, pp. 288-302. Click here for PDF version of paper.

Poulton, J., Dally, W., and Tell, T., "A Tracking Clock Recovery Receiver for 4Gb/S Signaling," Proceedings of Hot Interconnects V, Stanford University, Aug 21-23, 1997, pp. 157-169.

Eyles, J., S. Molnar, J. Poulton, T. Greer, A. Lastra, N. England, and L. Westover, "PixelFlow: The Realization," Proceedings of the 1997 Siggraph/Eurographics Workshop on Graphics Hardware, ACM Siggraph, pp. 57-68.

Poulton, J., "Gbit Signalling with CMOS," Invited presentation at 8th Workshop on Interconnections Within High Speed Digital Systems, IEEE LEOS, Santa Fe, NM, May 11-14, 1997.

Dally, W. J., and J. Poulton, " Transmitter Equalization for 4-GBPS Signaling," IEEE Micro, Jan/Feb 1997, pp 48-56. Also appeared in " Proceedings of IEEE Hot Interconnects IV," Aug 15-17, 1996, Stanford University.

Keller, K., and J. Poulton, "Commercial Packaging Solutions for a Research Oriented Graphics Supercomputer," Proc. of the 1995 Conference on Advances in Electronic Packaging, Vol 10-1, pp. 53-58.

Poulton, J., J. Eyles, and S. Molnar, "Breaking the Frame-Buffer Bottleneck with Logic-Enhanced Memories," IEEE Computer Graphics and Applications, November 1992, pp. 65-74.

Molnar, S., J. Eyles, and J. Poulton, "PixelFlow: High-Speed Rendering Using Image Composition," Computer Graphics (Proc. of SIGGRAPH '92), Vol. 26, No. 2, pp. 231-240.

Poulton, J., "Building Microelectronic Systems in a University Environment," Proc. of the 1991 Conference on Advanced Research in VLSI, (invited presentation) UC-Santa Cruz, March 25-27, 1991, p. 387-400.

Fuchs, H., Poulton, J., Eyles, J., Greer, T., Goldfeather, J., Ellsworth, D., Molnar, S., Turk, G., and Israel, L., "A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories," Computer Graphics (Proc. of SIGGRAPH '89), Vol. 23, No. 3, pp 79-88.

Fuchs, H., Poulton, J., Eyles, J., and Greer, T., "Coarse-Grain and Fine-Grain Parallelism in the Next Generation Pixel-Planes Graphics System," UNC-CS Tech Report TR88-014. Proc. of the International Conference and Exhibition on Parallel Processing for Computer Vision and Display, University of Leeds, UK, Jan. 12-15, 1988.

Eyles, J., Austin, J., Fuchs, H., Greer, T., and Poulton, J., "PIXEL-PLANES 4: A Summary," (presented at Eurographics '87, 2nd Workshop on Graphics Hardware), Advances in Graphics Hardware II, Springer-Verlag, 1988, pp. 183-207.

Poulton, J., Fuchs, H., Austin, J., Eyles, J. and Greer, T., "Building a 512x512 Pixel-planes System," Proceedings of the 1987 Stanford Conference on Advanced Research in VLSI, March 23-26, 1987. MIT Press, pp 57-71.

Fuchs, H., and Poulton, J., "Parallel Processing in Pixel-planes, A VLSI Logic-enhanced Memory for Raster Graphics," Proceedings of ICCD '85, October 7-10, 1985.

Poulton, J., Fuchs, H., Austin, J., Eyles, J., Heinecke, J., Hsieh, C-H, Goldfeather, J., Hultquist, J., and Spach, S., "PIXEL-PLANES: Building a VLSI-Based Graphic System," Proceedings of Conference on Advanced Research in VLSI, May 15-17, 1985, pp 35-60.

Fuchs, H., Goldfeather, J., Hultquist, J., Spach, S., Austin, J., Brooks, F., Eyles, J., and Poulton, J., "Fast Spheres, Shadows, Textures, Transparencies, and Image Enhancements in Pixel-Planes," Computer Graphics (SIGGRAPH '85 Conference Proceedings), Vol. 19, No. 3, July, 1985, pp 111-120.

Poulton, J., Fuchs, H., Paeth, A., "Pixel-planes Graphic Engine: A Case Study," in Principles of CMOS VLSI Design by Weste, N., and Eshraghian, K., Addison-Wesley, 1985, pp 448-480.

Rosenburg, J., Boyer, D., Dallen, J., Daniel, S., Poirier, C., Poulton, J., Rogers, D., and Weste, N., "A Vertically Integrated VLSI Design Environment," Proceedings of the 20th Design Automation Conference, 1983, pp 31-38. (Winner of Best Presentation Award).

Fuchs, H., Poulton, J., Paeth, A., and Bell, A., "Developing Pixel-planes, a Smart Memory-Based Raster Graphics System," Proceedings of Conference on Advanced Research in VLSI, January 25-27, 1982, pp 137-146.

Fuchs, H., and Poulton, J., "PIXEL-PLANES A VLSI-Oriented Design for a Raster Graphics Engine," VLSI Design (formerly Lambda - The Magazine of VLSI Design), Third quarter, 1981, pp 20-28.

Bear, R., Adams, J., and Poulton, J., "Disclosure by Fourier Methods of a Long-range Pattern of Non-polar Residues in the Alpha-1 (I) Sequence of Collagen," Journal of Molecular Biology, 1978, 118, pp 123-126.


J. Poulton, S. Tell, and R. Palmer, "Methods and Systems for Transmitting and Receiving Differential Signals over a Plurality of Conductors," Patent No. 6,556,628, April 29, 2003. Click here for PDF of white paper on this invention.

W. Dally, R. Farjad-Rad, T. Stone, X. Yu, and J. Poulton, "Low-Power Low-Jitter Variable Delay Timing Circuit," Patent No. 6,476,656, November 5, 2002.

W. Dally, R. Farjad, T. Stone, J. Yu, and J. Poulton, "Combined Phase Comparator and Charge Pump Circuit," Patent No. 6,275,072, August 2, 2001

J. Poulton, S. Molnar, J. Eyles, "Architecture and Apparatus for Image Generation," Patent No. 5,388,206, February 7, 1995 and No. 5,481,669, January 2, 1996.

H. Fuchs, and J. Poulton "VLSI Graphics Display Image Buffer Using Logic Enhanced Pixel Memory Cells," Patent No. 4,783,649, November 8, 1988.