Multicore-based hardware platforms are increasingly being used to implement computationally intensive safety-critical systems such as autonomous vehicles, robots, and smart medical devices. These systems often have components that require real-time certification. To this end, a “separation of concerns” strategy is applied: first, worst-case execution times (WCETs) for executable code are determined through a process called timing analysis; then, schedulability analysis is applied to validate timing constraints (usually deadlines) assuming valid WCET values are provided.
Unfortunately, there is consensus today that, on multicore platforms, the only viable approach for timing analysis is via measurement-based methods, which are fundamentally incapable of producing correct WCETs with certainty. This fact creates a disconnect with schedulability analysis that calls into question whether real-time safety can even be certified on multicore platforms. The goal of this project is to bridge this disconnect by using budget enforcement to ensure that WCET assumptions are respected at runtime. WCETs are ordinarily viewed as being task (program) parameters, but they are also needed for critical sections when real-time synchronization protocols are used, and for subsystems of a larger system when tasks are aggregated in some way, e.g., as nodes in a processing graph or as part of some system component. The need for budget enforcement at so many levels creates theoretical and practical problems that have never been addressed before.
This project will address the problems noted above through multifaceted research that focuses on (i) identifying those budgets that must be policed to enable real-time safety certification in multicore systems, (ii) examining the implications for scheduling and timing analysis that arise from making multi-level budget enforcement a first-class concern, and (iii) investigating implementation concerns for efficient and predictable multi-level budget enforcement. New research results will be produced regarding the orchestration of budget enforcement across (at least) four levels: components, processing graphs, tasks, and shared resources
The push to realize ever more sophisticated embedded systems, such as autonomous vehicles and aircraft, is being driven by the capabilities of multicore platforms. However, the disconnect that exists between timing analysis and scheduability analysis points to a looming certification crisis. If this crisis is not addressed, then it will not be possible to field systems that can be confidently viewed as safe. This project is directed at bridging this disconnect.
S. Ahmed and J. Anderson, " Optimal Multiprocessor Locking Protocols under FIFO Scheduling", Proceedings of the 35th Euromicro Conference on Real-Time Systems, July 2023, to appear. PDF .
J. Bakita and J. Anderson, " Hardware Compute Partitioning on NVIDIA GPUs", Proceedings of the 29th IEEE Real-Time and Embedded Technology and Applications Symposium, pp. 54–66, May 2023. PDF . Artifact evaluation instructions are here . Winner, outstanding paper award.
Last modified 31 May 2023