Multicore processors provide significant computational capacity within a restricted size, weight, and power (SWaP) envelope. As such, they are seen by many people as a key enabler for a wealth of new computationally intensive safety-critical embedded systems, such as autonomous aircraft and vehicles. However, safety-critical systems must be certified before being deployed, and certification procedures applicable to multicore-equipped systems are currently lacking. The key technical challenge that arises when using a multicore processor in a safety-critical setting is that of dealing with any interference that can occur when tasks executing on different cores access shared hardware resources such as caches, buses, and memory. Such interference can cause spikes in task execution times, resulting in timing-constraint violations.
The Navy, Army, and Air Force are currently involved in a joint initiative to confront these interference-related difficulties and devise certification procedures for multicore-equipped embedded systems. While this initiative pertains to safety-critical systems generally, avionics systems have been the preeminent focus. From a certification point of view, effectively dealing with interference, while still being able to reap the computational capacity that a multicore machine affords, is not easy. Perhaps because of this, the joint DoD initiative just mentioned has so far entirely focused on static (non-changing) workloads and CPU-only multicore platforms.
As this initiative progresses, it is inevitable that it must expand to include dynamically changing workloads and more heterogeneous hardware. The need for the former will be driven by the ever increasing levels of autonomy seen in aircraft: the very design of these aircraft entails dynamically reacting to changing conditions. Contrastingly, the need for accelerators is here now. Indeed, in avionics systems today, field programmable gate arrays (FPGAs), application-specific circuits (ASICs), and digital signal processors (DSPs) are commonly used as accelerators. Additionally, in more forward-looking autonomous systems, graphics processing units (GPUs) or other AI accelerators will likely be used to accelerate decision-making functions.
The specific outcome of this project will be a new real-time resource-allocation framework that allows tasks of varying criticalities to be co-hosted, with suitable isolation against interference in the face of dynamic workload changes, on a single heterogeneous multicore platform endowed with a variety of accelerators. This framework will be obtained through research involving five goals: (i) developing real-time arbitration mechanisms for policing access to accelerators; (ii) devising mechanisms for controlling accelerator-related data movement; (iii) devising mechanisms for increasing parallelism as tasks access disparate computational elements; (iv) developing accelerator-aware methods for enacting dynamic workload changes; and (v) conducting experimental evaluations. With respect to the latter, a 12-core PowerPC T4240, augmented with various FPGA, DSP, and GPU accelerators, will be the primary experimental platform.
The fact that all three DoD branches are working together to flesh out certification procedures for multicore-equipped avionics systems is proof of DoD interest in the topic of this project. In avionics, the case for using multicore machines—particularly augmented with accelerators—is perhaps strongest for envisioned autonomous aircraft, which will have enhanced “thinking” capabilities that will require significant computational resources.
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S. Ahmed and J. Anderson, " Tight Tardiness Bounds for Pseudo-Harmonic Tasks under Global-EDF-Like Schedulers", Proceedings of the 33rd Euromicro Conference on Real-Time Systems, July 2021, to appear. Winner, outstanding paper award. PDF .
T. Amert and J. Anderson, " CUPiDRT: Detecting Improper GPU Usage in Real-Time Applications", Proceedings of the 24th IEEE International Symposium on Real-Time Distributed Computing, June 2021. Winner, best paper award. pp. 278-291, May 2021. PDF .
J. Bakita, S. Ahmed, S. Osborne, S. Tang, J. Chen, F.D. Smith, and J. Anderson, " Simultaneous Multithreading in Mixed-Criticality Real-Time Systems", Proceedings of the 27th IEEE Real-Time and Embedded Technology and Applications Symposium, pp. 278-291, May 2021. PDF .
S. Tang, L. Abeni, and J. Anderson, " On the Defectiveness of SCHED_DEADLINE w.r.t. Tardiness and Affinities, and a Partial Fix", Proceedings of the 29th International Conference on Real-Time Networks and Systems, April 2021. PDF .
N. Otterness and J. Anderson, " Exploring AMD GPU Scheduling Details by Experimenting With `Worst Practices'", Proceedings of the 29th International Conference on Real-Time Networks and Systems, April 2021. Winner, best paper award. PDF .
D. Roy, C. Hobbs, J. Anderson, M. Caccamo and S. Chakraborty, " Timing Debugging for Cyber-Physical Systems", 2021 Design, Automation Test in Europe Conference Exhibition (DATE), February 2021. PDF .
C. Hobbs, D. Roy, P.S. Duggirala, F.D. Smith, S. Samii, J. Anderson, and S. Chakraborty, " Perception Computing-Aware Controller Synthesis for Autonomous Systems", 2021 Design, Automation Test in Europe Conference Exhibition (DATE), February 2021. PDF .
T. Amert, M. Balszun, M. Geier, F.D. Smith, J. Anderson, and S. Chakraborty, " Timing-Predictable Vision Processing for Autonomous Systems", 2021 Design, Automation Test in Europe Conference Exhibition (DATE), February 2021. PDF .
S. Tang and J. Anderson, " Towards Practical Multiprocessor EDF with Affinities", Proceedings of the 41st IEEE Real-Time Systems Symposium, pp. 89-101, December 2020. PDF .
S. Ahmed and J. Anderson, " A Soft-Real-Time Optimal Semi-Clustered Scheduler with a Constant Tardiness Bound", Proceedings of the 26th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, August 2020. PDF .
S. Osborne, S. Ahmed, S. Nandi, and J. Anderson, " Exploiting Simultaneous Multithreading in Priority-Driven Hard Real-Time Systems", Proceedings of the 26th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, August 2020. PDF .
N. Otterness and J. Anderson, " AMD GPUs as an Alternative to NVIDIA for Supporting Real-Time Workloads", Proceedings of the 32nd Euromicro Conference on Real-Time Systems, pp. 10:1-10:23, July 2020. PDF .
S. Osborne and J. Anderson, " Simultaneous Multithreading and Hard Real Time: Can it be Safe?", Proceedings of the 32nd Euromicro Conference on Real-Time Systems, pp. 14:1-14:25, July 2020. PDF .
T. Amert, M. Yang, S. Nandi, T. Vu, J. Anderson, and F.D. Smith, " The Price of Schedulability in Multi-Object Tracking: The History-vs.-Accuracy Trade-Off", Proceedings of the 23rd International Symposium on Real-Time Distributed Computing, pp. 124-133, May 2020. PDF .
Other papers that acknowledge this grant can be found on the PI's Publications Page .
Last modified 2 July 2021