Multicore processors provide significant computational capacity within a restricted size, weight, and power (SWaP) envelope. As such, they are seen by many people as a key enabler for a wealth of new computationally intensive safety-critical embedded systems, such as autonomous aircraft and vehicles. However, safety-critical systems must be certified before being deployed, and certification procedures applicable to multicore-equipped systems are currently lacking. The key technical challenge that arises when using a multicore processor in a safety-critical setting is that of dealing with any interference that can occur when tasks executing on different cores access shared hardware resources such as caches, buses, and memory. Such interference can cause spikes in task execution times, resulting in timing-constraint violations.
The Navy, Army, and Air Force are currently involved in a joint initiative to confront these interference-related difficulties and devise certification procedures for multicore-equipped embedded systems. While this initiative pertains to safety-critical systems generally, avionics systems have been the preeminent focus. From a certification point of view, effectively dealing with interference, while still being able to reap the computational capacity that a multicore machine affords, is not easy. Perhaps because of this, the joint DoD initiative just mentioned has so far entirely focused on static (non-changing) workloads and CPU-only multicore platforms.
As this initiative progresses, it is inevitable that it must expand to include dynamically changing workloads and more heterogeneous hardware. The need for the former will be driven by the ever increasing levels of autonomy seen in aircraft: the very design of these aircraft entails dynamically reacting to changing conditions. Contrastingly, the need for accelerators is here now. Indeed, in avionics systems today, field programmable gate arrays (FPGAs), application-specific circuits (ASICs), and digital signal processors (DSPs) are commonly used as accelerators. Additionally, in more forward-looking autonomous systems, graphics processing units (GPUs) or other AI accelerators will likely be used to accelerate decision-making functions.
The specific outcome of this project will be a new real-time resource-allocation framework that allows tasks of varying criticalities to be co-hosted, with suitable isolation against interference in the face of dynamic workload changes, on a single heterogeneous multicore platform endowed with a variety of accelerators. This framework will be obtained through research involving five goals: (i) developing real-time arbitration mechanisms for policing access to accelerators; (ii) devising mechanisms for controlling accelerator-related data movement; (iii) devising mechanisms for increasing parallelism as tasks access disparate computational elements; (iv) developing accelerator-aware methods for enacting dynamic workload changes; and (v) conducting experimental evaluations. With respect to the latter, a 12-core PowerPC T4240, augmented with various FPGA, DSP, and GPU accelerators, will be the primary experimental platform.
The fact that all three DoD branches are working together to flesh out certification procedures for multicore-equipped avionics systems is proof of DoD interest in the topic of this project. In avionics, the case for using multicore machines—particularly augmented with accelerators—is perhaps strongest for envisioned autonomous aircraft, which will have enhanced “thinking” capabilities that will require significant computational resources.
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Other papers that acknowledge this grant can be found on the PI's Publications Page .
Last modified 25 October 2019